Searched refs:divm (Results 1 – 2 of 2) sorted by relevance
1198 uint32_t divm = vco->div_mn[PLL_CFG_M]; in clk_stm32_pll_compute_cfgr1() local1204 refclk = prate / (divm + 1U); in clk_stm32_pll_compute_cfgr1()1218 *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK; in clk_stm32_pll_compute_cfgr1()1321 unsigned int divm; in clk_compute_pll1_settings() local1345 for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) { in clk_compute_pll1_settings()1346 unsigned long post_divm = input_freq / divm; in clk_compute_pll1_settings()1360 freq = output_freq * divm * (divp + 1U); in clk_compute_pll1_settings()1395 pll1->vco.div_mn[PLL_CFG_M] = divm - 1U; in clk_compute_pll1_settings()1706 uint32_t cfgr1, fracr, divm, divn; in clk_stm32_pll_recalc_rate() local1712 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; in clk_stm32_pll_recalc_rate()[all …]
1049 uint32_t cfgr1, fracr, divm, divn; in stm32mp1_pll_get_fvco() local1055 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; in stm32mp1_pll_get_fvco()1073 denominator = ((unsigned long long)divm + 1U) << 13; in stm32mp1_pll_get_fvco()1076 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); in stm32mp1_pll_get_fvco()1943 unsigned int divm; in clk_compute_pll1_settings() local1950 for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) { in clk_compute_pll1_settings()1951 unsigned long post_divm = input_freq / divm; in clk_compute_pll1_settings()1965 freq = output_freq * divm * (divp + 1U); in clk_compute_pll1_settings()1998 pllcfg[PLLCFG_M] = divm - 1U; in clk_compute_pll1_settings()