1198 	uint32_t divm = vco->div_mn[PLL_CFG_M];  in clk_stm32_pll_compute_cfgr1()  local
1204 	refclk = prate / (divm + 1U);  in clk_stm32_pll_compute_cfgr1()
1218 	*value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK;  in clk_stm32_pll_compute_cfgr1()
1321 	unsigned int divm;  in clk_compute_pll1_settings()  local
1345 	for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) {  in clk_compute_pll1_settings()
1346 		unsigned long post_divm = input_freq / divm;  in clk_compute_pll1_settings()
1360 			freq = output_freq * divm * (divp + 1U);  in clk_compute_pll1_settings()
1395 					pll1->vco.div_mn[PLL_CFG_M] = divm - 1U;  in clk_compute_pll1_settings()
1706 	uint32_t cfgr1, fracr, divm, divn;  in clk_stm32_pll_recalc_rate()  local
1712 	divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;  in clk_stm32_pll_recalc_rate()
1728 		denominator = ((unsigned long long)divm + 1U) << 13;  in clk_stm32_pll_recalc_rate()
1731 		fvco = (unsigned long)(prate * (divn + 1U) / (divm + 1U));  in clk_stm32_pll_recalc_rate()