Searched refs:csg (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32mp2.c | 38 uint32_t csg[PLLCSG_NB]; member
1698 uint32_t *csg) in clk_stm32_pll_config_csg() argument
1707 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); in clk_stm32_pll_config_csg()
1709 (csg[SPREAD] << RCC_PLLxCFGR5_SPREAD_SHIFT) & in clk_stm32_pll_config_csg()
1712 if (csg[DOWNSPREAD] != 0) { in clk_stm32_pll_config_csg()
1816 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg); in _clk_stm32_pll_init()
2367 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", (int)PLLCSG_NB, pll->csg); in clk_stm32_parse_pll_fdt()
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| H A D | stm32mp1_clk.c | 57 uint32_t csg[PLLCSG_NB]; member
1918 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) in stm32mp1_pll_csg() argument
1923 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & in stm32mp1_pll_csg()
1926 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & in stm32mp1_pll_csg()
1929 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & in stm32mp1_pll_csg()
2340 stm32mp1_pll_csg(i, pll_conf[i].csg); in stm32mp1_clk_init()
2680 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLLCSG_NB, pll->csg); in clk_stm32_load_vco_config()
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| H A D | clk-stm32mp13.c | 66 uint32_t csg[PLL_CSG_NB]; member
1271 mod_per = vco->csg[PLL_CSG_MOD_PER]; in clk_stm32_pll_config_csg()
1272 inc_step = vco->csg[PLL_CSG_INC_STEP]; in clk_stm32_pll_config_csg()
1273 sscg_mode = vco->csg[PLL_CSG_SSCG_MODE]; in clk_stm32_pll_config_csg()
2196 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg); in clk_stm32_load_vco_config()
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