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/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/
H A Dboot_init_dram_regdef.h24 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ argument
25 (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c176 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
190 col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
195 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c175 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
189 col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
194 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
218 col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
223 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Ddram.h122 unsigned char col; member
H A Ddram.c33 ch->col = SYS_REG_DEC_COL(os_reg2_val, i); in dram_init()
H A Dsuspend.c438 cs0_cap = (1 << (ch->cs0_row + ch->col + ch->bk + ch->bw - 20)); in set_ddrconfig()
461 if (sdram_params->ch[i].col == 0) in dram_all_config()
824 if (sdram_params->ch[channel].col) in dmc_resume()
H A Ddfs.c95 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + in get_cs_die_capability()
/rk3399_ARM-atf/tools/memory/src/memory/
H A Dsummary.py462 for col in self.print_sections:
463 table.align[col] = "r"