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Searched refs:WDT0_BASE (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Daddressmap_shared.h44 #define WDT0_BASE (MMIO_BASE + 0x07848000) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c680 mmio_write_32(WDT0_BASE + 4, 0x9); in pmusram_enable_watchdog()
683 mmio_setbits_32(WDT0_BASE, 0x1); in pmusram_enable_watchdog()
686 mmio_write_32(WDT0_BASE + 0xc, 0x76); in pmusram_enable_watchdog()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dpmu.c1324 store_wdt0[i] = mmio_read_32(WDT0_BASE + i * 4); in wdt_register_save()
1335 mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]); in wdt_register_restore()
1340 mmio_write_32(WDT0_BASE + 0x0c, 0x76); in wdt_register_restore()