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Searched refs:PMUGRF_BASE (Results 1 – 11 of 11) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pwm/
H A Dpwm.c52 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX); in disable_pwms()
58 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); in disable_pwms()
61 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX); in disable_pwms()
67 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); in disable_pwms()
100 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); in enable_pwms()
107 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); in enable_pwms()
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c584 mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_CON0); in pvtm_32k_config()
586 mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_CON1); in pvtm_32k_config()
588 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0, in pvtm_32k_config()
591 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0, in pvtm_32k_config()
594 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON1, PVTM_CALC_CNT); in pvtm_32k_config()
597 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0, in pvtm_32k_config()
604 while (mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST1) < 30) in pvtm_32k_config()
608 while (!(mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST0) & 0x1)) in pvtm_32k_config()
612 (mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST1) * 24000 + in pvtm_32k_config()
625 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0, in pvtm_32k_config()
[all …]
/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.c95 tmp = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(3)); in soc_reset_config_all()
97 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), tmp); in soc_reset_config_all()
124 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(2), in px30_soc_reset_config()
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h23 #define PMUGRF_BASE 0xfdc20000 macro
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c62 mmio_write_32(PMUGRF_BASE + PMU_GRF_SOC_CON(0), WRITE_MASK_SET(BIT(7))); in pmu_pmic_sleep_mode_config()
63 mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_IOMUX_L, PMIC_SLEEP_FUN); in pmu_pmic_sleep_mode_config()
306 mmio_write_32(PMUGRF_BASE + PMU_GRF_DLL_CON0, pvtm_div); in pvtm_32k_config()
530 mmio_write_32(PMUGRF_BASE + PMU_GRF_SOC_CON(0), 0x00800080); in plat_rockchip_pmu_init()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Ddram.c19 os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); in dram_init()
H A Ddfs.c1745 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & in exit_low_power()
1783 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & in resume_low_power()
/rk3399_ARM-atf/plat/rockchip/px30/
H A Dpx30_def.h24 #define PMUGRF_BASE 0xff010000 macro
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Daddressmap_shared.h27 #define PMUGRF_BASE (MMIO_BASE + 0x07320000) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/
H A Drk3399_gpio.c80 .pull_base = PMUGRF_BASE + PMUGRF_GPIO0A_P,
87 .pull_base = PMUGRF_BASE + PMUGRF_GPIO1A_P,
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dpmu.c891 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K); in sys_slp_config()
892 mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */ in sys_slp_config()
1550 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, in rockchip_soc_system_off()
1618 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE); in plat_rockchip_pmu_init()