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Searched refs:MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/dcm/
H A Dmtk_dcm_utils.c298 ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) & in dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on()
309 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm()
314 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm()
H A Dmtk_dcm_utils.h23 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) macro
/rk3399_ARM-atf/plat/mediatek/drivers/dcm/
H A Dmtk_dcm_utils.c236 return dcm_check_state(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on()
245 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm()
250 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm()
H A Dmtk_dcm_utils.h22 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dcm/
H A Dmtk_dcm_utils.h21 #define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4) macro
H A Dmtk_dcm_utils.c280 ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) & in dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on()
291 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm()
296 mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1, in dcm_mp_cpusys_top_cpu_pll_div_1_dcm()