Searched refs:HW_DRAM_PLL_CFG0 (Results 1 – 2 of 2) sorted by relevance
61 mmio_setbits_32(HW_DRAM_PLL_CFG0, 0x30); in dram_pll_init()78 mmio_clrbits_32(HW_DRAM_PLL_CFG0, 0x30); in dram_pll_init()79 while (!(mmio_read_32(HW_DRAM_PLL_CFG0) & BIT(31))) { in dram_pll_init()
144 #define HW_DRAM_PLL_CFG0 (IMX_ANAMIX_BASE + 0x60) macro147 #define DRAM_PLL_CTRL HW_DRAM_PLL_CFG0