| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/ |
| H A D | pmu.c | 849 mmio_write_32(GRF_BASE + GRF_SOC_CON4, CCI_FORCE_WAKEUP); in sys_slp_config()
922 iomux_status[i] = mmio_read_32(GRF_BASE + in suspend_apio()
924 pull_mode_status[i] = mmio_read_32(GRF_BASE + in suspend_apio()
945 mmio_write_32(GRF_BASE + GRF_GPIO3A_IOMUX, in suspend_apio()
947 mmio_write_32(GRF_BASE + GRF_GPIO3B_IOMUX, in suspend_apio()
949 mmio_write_32(GRF_BASE + GRF_GPIO3C_IOMUX, in suspend_apio()
953 mmio_write_32(GRF_BASE + GRF_GPIO3A_P, REG_SOC_WMSK | 0); in suspend_apio()
954 mmio_write_32(GRF_BASE + GRF_GPIO3B_P, REG_SOC_WMSK | 0); in suspend_apio()
955 mmio_write_32(GRF_BASE + GRF_GPIO3C_P, REG_SOC_WMSK | 0); in suspend_apio()
965 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX, in suspend_apio()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pwm/ |
| H A D | pwm.c | 34 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); in disable_pwms()
40 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in disable_pwms()
43 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); in disable_pwms()
49 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in disable_pwms()
114 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in enable_pwms()
121 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in enable_pwms()
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/ |
| H A D | rk3399_gpio.c | 94 .pull_base = GRF_BASE + GRF_GPIO2A_P,
101 .pull_base = GRF_BASE + GRF_GPIO3A_P,
108 .pull_base = GRF_BASE + GRF_GPIO4A_P,
348 mmio_read_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4); in plat_rockchip_save_gpio()
357 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4, in plat_rockchip_restore_gpio()
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| /rk3399_ARM-atf/plat/rockchip/rk3368/ |
| H A D | rk3368_def.h | 25 #define GRF_BASE 0xff770000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/ |
| H A D | pmu.c | 221 val = mmio_read_32(GRF_BASE + GRF_GPIO2D_IOMUX); in rockchip_soc_system_off()
223 mmio_write_32(GRF_BASE + GRF_GPIO2D_IOMUX, val); in rockchip_soc_system_off()
471 sram_data.pmic_sleep_save = mmio_read_32(GRF_BASE + PMIC_SLEEP_REG); in rk3328_pmic_suspend()
474 mmio_write_32(GRF_BASE + PMIC_SLEEP_REG, BITS_WITH_WMASK(0, 0x3, 4)); in rk3328_pmic_suspend()
485 mmio_write_32(GRF_BASE + PMIC_SLEEP_REG, in rk3328_pmic_resume()
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| H A D | pmu.h | 69 #define CHECK_CPU_WFIE_BASE (GRF_BASE + GRF_CPU_STATUS(1))
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| /rk3399_ARM-atf/plat/rockchip/rk3568/ |
| H A D | rk3568_def.h | 27 #define GRF_BASE 0xfdc60000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3288/ |
| H A D | rk3288_def.h | 63 #define GRF_BASE 0xff770000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/soc/ |
| H A D | soc.c | 90 mmio_write_32(GRF_BASE + 0x0508, 0x00100010); in rockchip_system_reset_init()
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| /rk3399_ARM-atf/plat/rockchip/rk3328/ |
| H A D | rk3328_def.h | 36 #define GRF_BASE 0xff100000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/ |
| H A D | rk3568_clk.c | 503 mmio_write_32(GRF_BASE + RK3568_GPU_PVTPLL_CON0, in clk_gpu_set_rate()
506 mmio_write_32(GRF_BASE + RK3568_GPU_PVTPLL_CON0, in clk_gpu_set_rate()
570 mmio_write_32(GRF_BASE + RK3568_NPU_PVTPLL_CON0, in clk_npu_set_rate()
573 mmio_write_32(GRF_BASE + RK3568_NPU_PVTPLL_CON0, in clk_npu_set_rate()
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| /rk3399_ARM-atf/plat/rockchip/px30/ |
| H A D | px30_def.h | 49 #define GRF_BASE 0xff140000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/ |
| H A D | addressmap_shared.h | 39 #define GRF_BASE (MMIO_BASE + 0x07770000) macro
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| /rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/ |
| H A D | soc.c | 100 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), in soc_reset_config_all()
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| /rk3399_ARM-atf/plat/rockchip/rk3368/drivers/ddr/ |
| H A D | ddr_rk3368.c | 383 p_ddr_reg->phypllockaddr = GRF_BASE + GRF_SOC_STATUS0; in ddr_reg_save()
430 p_ddr_reg->grfregaddr = GRF_BASE + GRF_DDRC0_CON0; in ddr_reg_save()
431 p_ddr_reg->grfddrcreg = (mmio_read_32(GRF_BASE + GRF_DDRC0_CON0) & in ddr_reg_save()
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| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.c | 42 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
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| /rk3399_ARM-atf/plat/rockchip/rk3288/drivers/pmu/ |
| H A D | pmu.c | 51 reg = mmio_read_32(GRF_BASE + reg_offset[i]); in rk3288_sleep_disable_osc()
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| /rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/ |
| H A D | soc.c | 49 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
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| /rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/ |
| H A D | soc.c | 49 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | dfs.c | 1821 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, in dram_low_power_config()
1828 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, in dram_low_power_config()
1874 mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); in dram_dfs_init()
1875 mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); in dram_dfs_init()
1876 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); in dram_dfs_init()
1877 mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); in dram_dfs_init()
1878 mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); in dram_dfs_init()
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| /rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/ |
| H A D | pmu.c | 373 while (!(mmio_read_32(GRF_BASE + GRF_CPU_STATUS1) & wfie_msk) && in check_cpu_wfie()
379 if ((mmio_read_32(GRF_BASE + GRF_CPU_STATUS1) & wfie_msk) == 0) { in check_cpu_wfie()
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