Searched refs:GPC_PU_PWRHSK (Results 1 – 8 of 8) sorted by relevance
| /rk3399_ARM-atf/plat/imx/imx8m/imx8mm/ |
| H A D | gpc.c | 211 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
214 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
221 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
224 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
229 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
232 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
245 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU2D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
248 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU2D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
252 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, GPU3D_ADB400_SYNC); in imx_gpc_pm_domain_enable()
255 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & GPU3D_ADB400_ACK)) { in imx_gpc_pm_domain_enable()
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mn/ |
| H A D | gpc.c | 100 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
103 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
118 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
121 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) { in imx_gpc_pm_domain_enable()
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| /rk3399_ARM-atf/plat/imx/imx8m/ddr/ |
| H A D | dram_retention.c | 104 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC); in dram_enter_retention()
105 while (mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & DDRMIX_ADB400_ACK) in dram_enter_retention()
107 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC); in dram_enter_retention()
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mp/ |
| H A D | gpc.c | 236 mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
239 while (!(mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
261 mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, pwr_domain->adb400_sync); in imx_gpc_pm_domain_enable()
264 while ((mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & pwr_domain->adb400_ack)) in imx_gpc_pm_domain_enable()
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mq/include/ |
| H A D | gpc_reg.h | 24 #define GPC_PU_PWRHSK 0x1FC macro
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mn/include/ |
| H A D | gpc_reg.h | 24 #define GPC_PU_PWRHSK 0x1FC macro
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mm/include/ |
| H A D | gpc_reg.h | 24 #define GPC_PU_PWRHSK 0x1FC macro
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mp/include/ |
| H A D | gpc_reg.h | 25 #define GPC_PU_PWRHSK 0x190 macro
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