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Searched refs:DFD_INTERNAL_CTL (Results 1 – 12 of 12) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/dfd/mt8188/
H A Dplat_dfd.c25 sync_writel(DFD_INTERNAL_CTL, 0x5); in dfd_setup()
26 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); in dfd_setup()
27 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); in dfd_setup()
28 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); in dfd_setup()
29 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
71 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
H A Dplat_dfd.h28 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dfd/
H A Dplat_dfd.c33 sync_writel(DFD_INTERNAL_CTL, 0x5); in dfd_setup()
36 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); in dfd_setup()
46 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1F << 3); in dfd_setup()
52 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 9); in dfd_setup()
55 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
115 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
H A Dplat_dfd.h31 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/dfd/
H A Dplat_dfd.c22 sync_writel(DFD_INTERNAL_CTL, 0x5); in dfd_setup()
25 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); in dfd_setup()
35 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3); in dfd_setup()
38 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
99 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
H A Dplat_dfd.h24 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/dfd/
H A Dplat_dfd.c24 sync_writel(DFD_INTERNAL_CTL, (BIT(0) | BIT(2))); in dfd_setup()
26 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(13)); in dfd_setup()
27 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(3)); in dfd_setup()
28 mmio_setbits_32(DFD_INTERNAL_CTL, (BIT(19) | BIT(20))); in dfd_setup()
57 mmio_setbits_32(DFD_INTERNAL_CTL, BIT(4)); in dfd_setup()
H A Dplat_dfd.h25 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) macro
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_debug.c36 sync_writel(DFD_INTERNAL_CTL, 0x1); in circular_buffer_unlock()
42 sync_writel(DFD_INTERNAL_CTL, 0x0); in circular_buffer_lock()
/rk3399_ARM-atf/plat/mediatek/mt8183/include/
H A Dplat_debug.h16 #define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00) macro
/rk3399_ARM-atf/plat/mediatek/drivers/dfd/mt8189/
H A Dplat_dfd.c18 { DFD_INTERNAL_CTL, 0x0018200D },
H A Dplat_dfd.h24 #define DFD_INTERNAL_CTL (MCU_BIU_BASE + 0XE040) macro