1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_DFD_H 8 #define PLAT_DFD_H 9 10 #include <lib/mmio.h> 11 #include <platform_def.h> 12 13 #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); dsbsy(); } while (0) 14 15 #define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150) 16 #define PLAT_MTK_DFD_READ_MAGIC (0x99716151) 17 #define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152) 18 19 #define MCU_BIU_BASE (MCUCFG_BASE) 20 #define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040) 21 #define DFD_CTRL (MCU_BIU_BASE + 0X8040) 22 #define DFD_CNT_L (MCU_BIU_BASE + 0X8044) 23 #define DFD_CNT_H (MCU_BIU_BASE + 0X8048) 24 #define DFD_INTERNAL_CTL (MCU_BIU_BASE + 0XE040) 25 #define DFD_INTERNAL_COUNTER (MCU_BIU_BASE + 0XE044) 26 #define DFD_INTERNAL_PWR_ON (MCU_BIU_BASE + 0XE048) 27 #define DFD_INTERNAL_CHAIN_LENGTH_0 (MCU_BIU_BASE + 0XE04C) 28 #define DFD_INTERNAL_SHIFT_CLK_RATIO (MCU_BIU_BASE + 0XE050) 29 #define DFD_INTERNAL_COUNTER_RETURN (MCU_BIU_BASE + 0XE054) 30 #define DFD_INTERNAL_SRAM_ACCESS (MCU_BIU_BASE + 0XE058) 31 #define DFD_FINISH_WAIT_TIME (MCU_BIU_BASE + 0XE05C) 32 #define DFD_INTERNAL_CHAIN_GROUP (MCU_BIU_BASE + 0XE060) 33 #define DFD_INTERNAL_CHAIN_INV_INFO_LL (MCU_BIU_BASE + 0XE064) 34 #define DFD_INTERNAL_CHAIN_INV_INFO_LH (MCU_BIU_BASE + 0XE068) 35 #define DFD_INTERNAL_CHAIN_INV_INFO_HL (MCU_BIU_BASE + 0XE06C) 36 #define DFD_INTERNAL_CHAIN_INV_INFO_HH (MCU_BIU_BASE + 0XE070) 37 #define DFD_INTERNAL_TEST_SO_OVER_64 (MCU_BIU_BASE + 0XE074) 38 #define DFD_INTERNAL_MASK_OUT (MCU_BIU_BASE + 0XE078) 39 #define DFD_INTERNAL_SW_NS_TRIGGER (MCU_BIU_BASE + 0XE07C) 40 #define DFD_INTERNAL_MCSI (MCU_BIU_BASE + 0XE080) 41 #define DFD_INTERNAL_MCSI_SEL_STATUS (MCU_BIU_BASE + 0XE084) 42 #define DFD_V30_CTL (MCU_BIU_BASE + 0XE088) 43 #define DFD_POWER_CTL (MCU_BIU_BASE + 0XE090) 44 #define DFD_RESET_ON (MCU_BIU_BASE + 0XE094) 45 #define DFD_TEST_SI_0 (MCU_BIU_BASE + 0XE098) 46 #define DFD_TEST_SI_1 (MCU_BIU_BASE + 0XE09C) 47 #define DFD_STATUS_CLEAN (MCU_BIU_BASE + 0XE0A0) 48 #define DFD_STATUS_RETURN (MCU_BIU_BASE + 0XE0A4) 49 #define DFD_V35_ENABLE (MCU_BIU_BASE + 0XE0A8) 50 #define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0XE0AC) 51 #define DFD_V35_TAP_EN (MCU_BIU_BASE + 0XE0B0) 52 #define DFD_V35_CTL (MCU_BIU_BASE + 0XE0B4) 53 #define DFD_V35_TAP_SEQ0 (MCU_BIU_BASE + 0XE0B8) 54 #define DFD_V35_TAP_SEQ1 (MCU_BIU_BASE + 0XE0BC) 55 #define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0XE0C0) 56 #define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0XE0C4) 57 #define DFD_V35_SEQ1_0 (MCU_BIU_BASE + 0XE0C8) 58 #define DFD_V35_SEQ1_1 (MCU_BIU_BASE + 0XE0CC) 59 #define DFD_V35_SEQ2_0 (MCU_BIU_BASE + 0XE0D0) 60 #define DFD_V35_SEQ2_1 (MCU_BIU_BASE + 0XE0D4) 61 #define DFD_SOC_CLOCK_STOP_MASK (MCU_BIU_BASE + 0XE0F0) 62 #define DFD_HW_TRIGGER_MASK (MCU_BIU_BASE + 0XE0FC) 63 #define DFD_V50_ENABLE (MCU_BIU_BASE + 0XE100) 64 #define DFD_V50_SELF_TRIGGER_ITERATION (MCU_BIU_BASE + 0XE104) 65 #define DFD_V50_START_TRIGGER (MCU_BIU_BASE + 0XE108) 66 #define DFD_V50_CPUCK_HALT (MCU_BIU_BASE + 0XE10C) 67 #define DFD_V50_26M_RESUME (MCU_BIU_BASE + 0XE110) 68 #define DFD_V50_26M_HALT_RELEASE (MCU_BIU_BASE + 0XE114) 69 #define DFD_V50_SYSTEM_HALT_TIME (MCU_BIU_BASE + 0XE118) 70 #define DFD_V50_GROUP_0_1_DIFF (MCU_BIU_BASE + 0XE11C) 71 #define DFD_V50_GROUP_0_2_DIFF (MCU_BIU_BASE + 0XE120) 72 #define DFD_V50_GROUP_0_3_DIFF (MCU_BIU_BASE + 0XE124) 73 #define DFD_V50_GROUP_0_4_DIFF (MCU_BIU_BASE + 0XE128) 74 #define DFD_V50_GROUP_0_5_DIFF (MCU_BIU_BASE + 0XE12C) 75 #define DFD_V50_GROUP_0_6_DIFF (MCU_BIU_BASE + 0XE130) 76 #define DFD_V50_GROUP_0_7_DIFF (MCU_BIU_BASE + 0XE134) 77 #define DFD_V50_GROUP_0_8_DIFF (MCU_BIU_BASE + 0XE138) 78 #define DFD_V50_GROUP_0_9_DIFF (MCU_BIU_BASE + 0XE13C) 79 #define DFD_V50_GROUP_0_10_DIFF (MCU_BIU_BASE + 0XE140) 80 #define DFD_V50_GROUP_0_11_DIFF (MCU_BIU_BASE + 0XE144) 81 #define DFD_V50_GROUP_0_12_DIFF (MCU_BIU_BASE + 0XE148) 82 #define DFD_V50_GROUP_0_13_DIFF (MCU_BIU_BASE + 0XE14C) 83 #define DFD_V50_GROUP_0_14_DIFF (MCU_BIU_BASE + 0XE150) 84 #define DFD_V50_GROUP_0_15_DIFF (MCU_BIU_BASE + 0XE154) 85 #define DFD_V50_GROUP_0_16_DIFF (MCU_BIU_BASE + 0XE158) 86 #define DFD_V50_GROUP_0_17_DIFF (MCU_BIU_BASE + 0XE15C) 87 #define DFD_V50_GROUP_0_18_DIFF (MCU_BIU_BASE + 0XE160) 88 #define DFD_V50_GROUP_0_19_DIFF (MCU_BIU_BASE + 0XE164) 89 #define DFD_V50_GROUP_0_20_DIFF (MCU_BIU_BASE + 0XE168) 90 #define DFD_V50_GROUP_0_21_DIFF (MCU_BIU_BASE + 0XE16C) 91 #define DFD_V50_GROUP_0_22_DIFF (MCU_BIU_BASE + 0XE170) 92 #define DFD_V50_GROUP_0_23_DIFF (MCU_BIU_BASE + 0XE174) 93 #define DFD_V50_GROUP_0_24_DIFF (MCU_BIU_BASE + 0XE178) 94 #define DFD_V50_GROUP_0_25_DIFF (MCU_BIU_BASE + 0XE17C) 95 #define DFD_V50_GROUP_0_26_DIFF (MCU_BIU_BASE + 0XE180) 96 #define DFD_V50_GROUP_0_27_DIFF (MCU_BIU_BASE + 0XE184) 97 #define DFD_V50_GROUP_0_28_DIFF (MCU_BIU_BASE + 0XE188) 98 #define DFD_V50_GROUP_0_29_DIFF (MCU_BIU_BASE + 0XE18C) 99 #define DFD_V50_GROUP_0_30_DIFF (MCU_BIU_BASE + 0XE190) 100 #define DFD_V50_GROUP_0_31_DIFF (MCU_BIU_BASE + 0XE194) 101 #define DFD_V50_CHAIN_GROUP_3_0_INFO (MCU_BIU_BASE + 0XE198) 102 #define DFD_V50_CHAIN_GROUP_7_4_INFO (MCU_BIU_BASE + 0XE19C) 103 #define DFD_V50_CHAIN_GROUP_11_8_INFO (MCU_BIU_BASE + 0XE1A0) 104 #define DFD_V50_CHAIN_GROUP_15_12_INFO (MCU_BIU_BASE + 0XE1A4) 105 #define DFD_V50_CHAIN_GROUP_19_16_INFO (MCU_BIU_BASE + 0XE1A8) 106 #define DFD_V50_CHAIN_GROUP_23_20_INFO (MCU_BIU_BASE + 0XE1AC) 107 #define DFD_V50_CHAIN_GROUP_27_24_INFO (MCU_BIU_BASE + 0XE1B0) 108 #define DFD_V50_CHAIN_GROUP_31_28_INFO (MCU_BIU_BASE + 0XE1B4) 109 #define DFD_V50_CHAIN_GROUP_35_32_INFO (MCU_BIU_BASE + 0XE1B8) 110 #define DFD_V50_CHAIN_GROUP_39_36_INFO (MCU_BIU_BASE + 0XE1BC) 111 #define DFD_V50_CHAIN_GROUP_43_40_INFO (MCU_BIU_BASE + 0XE1C0) 112 #define DFD_V50_CHAIN_GROUP_47_44_INFO (MCU_BIU_BASE + 0XE1C4) 113 #define DFD_V50_CHAIN_GROUP_51_48_INFO (MCU_BIU_BASE + 0XE1C8) 114 #define DFD_V50_CHAIN_GROUP_55_52_INFO (MCU_BIU_BASE + 0XE1CC) 115 #define DFD_V50_CHAIN_GROUP_59_56_INFO (MCU_BIU_BASE + 0XE1D0) 116 #define DFD_V50_CHAIN_GROUP_63_60_INFO (MCU_BIU_BASE + 0XE1D4) 117 #define DFD_V50_CHAIN_GROUP_67_64_INFO (MCU_BIU_BASE + 0XE1D8) 118 #define DFD_V50_CHAIN_GROUP_71_68_INFO (MCU_BIU_BASE + 0XE1DC) 119 #define DFD_V50_CHAIN_GROUP_75_72_INFO (MCU_BIU_BASE + 0XE1E0) 120 #define DFD_V50_CHAIN_GROUP_79_76_INFO (MCU_BIU_BASE + 0XE1E4) 121 #define DFD_V50_CHAIN_GROUP_83_80_INFO (MCU_BIU_BASE + 0XE1E8) 122 #define DFD_V50_CHAIN_GROUP_87_84_INFO (MCU_BIU_BASE + 0XE1EC) 123 #define DFD_V50_CHAIN_GROUP_91_88_INFO (MCU_BIU_BASE + 0XE1F0) 124 #define DFD_V50_CHAIN_GROUP_95_92_INFO (MCU_BIU_BASE + 0XE1F4) 125 #define DFD_V50_CHAIN_GROUP_99_96_INFO (MCU_BIU_BASE + 0XE1F8) 126 #define DFD_V50_CHAIN_GROUP_103_100_INFO (MCU_BIU_BASE + 0XE1FC) 127 #define DFD_V50_CHAIN_GROUP_107_104_INFO (MCU_BIU_BASE + 0XE200) 128 #define DFD_V50_CHAIN_GROUP_111_108_INFO (MCU_BIU_BASE + 0XE204) 129 #define DFD_V50_CHAIN_GROUP_115_112_INFO (MCU_BIU_BASE + 0XE208) 130 #define DFD_V50_CHAIN_GROUP_119_116_INFO (MCU_BIU_BASE + 0XE20C) 131 #define DFD_V50_CHAIN_GROUP_123_120_INFO (MCU_BIU_BASE + 0XE210) 132 #define DFD_V50_CHAIN_GROUP_127_124_INFO (MCU_BIU_BASE + 0XE214) 133 #define DFD_TEST_SI_2 (MCU_BIU_BASE + 0XE218) 134 #define DFD_TEST_SI_3 (MCU_BIU_BASE + 0XE21C) 135 #define DFD_TEST_SO (MCU_BIU_BASE + 0XE220) 136 #define DFD_BUS_HALT_TIME (MCU_BIU_BASE + 0XE224) 137 #define DFD_READ_ADDR (MCU_BIU_BASE + 0XE228) 138 #define DFD_V50_CLK_STOP_TIME (MCU_BIU_BASE + 0XE22C) 139 #define DFD_V50_GROUP_0_32_DIFF (MCU_BIU_BASE + 0XE230) 140 #define DFD_V50_GROUP_0_33_DIFF (MCU_BIU_BASE + 0XE234) 141 #define DFD_V50_GROUP_0_34_DIFF (MCU_BIU_BASE + 0XE238) 142 #define DFD_V50_GROUP_0_35_DIFF (MCU_BIU_BASE + 0XE23C) 143 #define DFD_V50_GROUP_0_36_DIFF (MCU_BIU_BASE + 0XE240) 144 #define DFD_V50_GROUP_0_37_DIFF (MCU_BIU_BASE + 0XE244) 145 #define DFD_V50_GROUP_0_38_DIFF (MCU_BIU_BASE + 0XE248) 146 #define DFD_V50_GROUP_0_39_DIFF (MCU_BIU_BASE + 0XE24C) 147 #define DFD_V50_GROUP_0_40_DIFF (MCU_BIU_BASE + 0XE250) 148 #define DFD_V50_GROUP_0_41_DIFF (MCU_BIU_BASE + 0XE254) 149 #define DFD_V50_GROUP_0_42_DIFF (MCU_BIU_BASE + 0XE258) 150 #define DFD_V50_GROUP_0_43_DIFF (MCU_BIU_BASE + 0XE25C) 151 #define DFD_V50_GROUP_0_44_DIFF (MCU_BIU_BASE + 0XE260) 152 #define DFD_V50_GROUP_0_45_DIFF (MCU_BIU_BASE + 0XE264) 153 #define DFD_V50_GROUP_0_46_DIFF (MCU_BIU_BASE + 0XE268) 154 #define DFD_V50_GROUP_0_47_DIFF (MCU_BIU_BASE + 0XE26C) 155 #define DFD_V50_GROUP_0_48_DIFF (MCU_BIU_BASE + 0XE270) 156 #define DFD_V50_GROUP_0_49_DIFF (MCU_BIU_BASE + 0XE274) 157 #define DFD_V50_GROUP_0_50_DIFF (MCU_BIU_BASE + 0XE278) 158 #define DFD_V50_GROUP_0_51_DIFF (MCU_BIU_BASE + 0XE27C) 159 #define DFD_V50_GROUP_0_52_DIFF (MCU_BIU_BASE + 0XE280) 160 #define DFD_V50_GROUP_0_53_DIFF (MCU_BIU_BASE + 0XE284) 161 #define DFD_V50_GROUP_0_54_DIFF (MCU_BIU_BASE + 0XE288) 162 #define DFD_V50_GROUP_0_55_DIFF (MCU_BIU_BASE + 0XE28C) 163 #define DFD_V50_GROUP_0_56_DIFF (MCU_BIU_BASE + 0XE290) 164 #define DFD_V50_GROUP_0_57_DIFF (MCU_BIU_BASE + 0XE294) 165 #define DFD_V50_GROUP_0_58_DIFF (MCU_BIU_BASE + 0XE298) 166 #define DFD_V50_GROUP_0_59_DIFF (MCU_BIU_BASE + 0XE29C) 167 #define DFD_V50_GROUP_0_60_DIFF (MCU_BIU_BASE + 0XE2A0) 168 #define DFD_V50_GROUP_0_61_DIFF (MCU_BIU_BASE + 0XE2A4) 169 #define DFD_V50_GROUP_0_62_DIFF (MCU_BIU_BASE + 0XE2A8) 170 #define DFD_V50_GROUP_0_63_DIFF (MCU_BIU_BASE + 0XE2AC) 171 172 #define DFD_O_PROTECT_EN_REG (0x10001220) 173 #define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C) 174 #define DFD_O_SET_BASEADDR_REG (0x10043010) 175 #define DFD_O_REG_0 (0x10001390) 176 177 #define DFD_CACHE_DUMP_ENABLE (1U) 178 179 #define DFD_V35_TAP_EN_VAL (0x43FF) 180 #define DFD_V35_SEQ0_0_VAL (0x63668820) 181 #define DFD_READ_ADDR_VAL (0x40000008) 182 #define DFD_CHAIN_LENGTH_VAL (0xFFFFFFFF) 183 184 #endif /* PLAT_DFD_H */ 185