Searched refs:DBSC4_REG_DBPDRGA0 (Results 1 – 1 of 1) sorted by relevance
60 #define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U) macro555 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0); in rcar_pwrc_set_self_refresh_e3()559 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR); in rcar_pwrc_set_self_refresh_e3()563 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1); in rcar_pwrc_set_self_refresh_e3()567 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1); in rcar_pwrc_set_self_refresh_e3()571 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3); in rcar_pwrc_set_self_refresh_e3()575 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5); in rcar_pwrc_set_self_refresh_e3()579 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2); in rcar_pwrc_set_self_refresh_e3()583 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2); in rcar_pwrc_set_self_refresh_e3()587 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2); in rcar_pwrc_set_self_refresh_e3()[all …]