60 #define DBSC4_REG_DBPDRGA0			(DBSC4_REG_BASE + 0x0624U)  macro
555 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0);  in rcar_pwrc_set_self_refresh_e3()
559 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR);  in rcar_pwrc_set_self_refresh_e3()
563 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1);  in rcar_pwrc_set_self_refresh_e3()
567 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1);  in rcar_pwrc_set_self_refresh_e3()
571 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3);  in rcar_pwrc_set_self_refresh_e3()
575 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5);  in rcar_pwrc_set_self_refresh_e3()
579 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2);  in rcar_pwrc_set_self_refresh_e3()
583 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2);  in rcar_pwrc_set_self_refresh_e3()
587 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2);  in rcar_pwrc_set_self_refresh_e3()
591 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2);  in rcar_pwrc_set_self_refresh_e3()
595 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR);  in rcar_pwrc_set_self_refresh_e3()
602 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0);  in rcar_pwrc_set_self_refresh_e3()
606 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0);  in rcar_pwrc_set_self_refresh_e3()
610 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0);  in rcar_pwrc_set_self_refresh_e3()
614 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0);  in rcar_pwrc_set_self_refresh_e3()
618 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1);  in rcar_pwrc_set_self_refresh_e3()
622 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1);  in rcar_pwrc_set_self_refresh_e3()
626 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1);  in rcar_pwrc_set_self_refresh_e3()
630 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1);  in rcar_pwrc_set_self_refresh_e3()
634 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3);  in rcar_pwrc_set_self_refresh_e3()
638 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3);  in rcar_pwrc_set_self_refresh_e3()
642 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3);  in rcar_pwrc_set_self_refresh_e3()
646 	mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3);  in rcar_pwrc_set_self_refresh_e3()