| #
b8ad1a16 |
| 16-Oct-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(rcar): deduplicate PWRC timer" into integration
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| #
92196d4f |
| 27-Sep-2025 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
feat(rcar): deduplicate PWRC timer
The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mai
feat(rcar): deduplicate PWRC timer
The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Id50a730ea58faedaa24380fd3171be171ecd7269
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| #
5b096283 |
| 05-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration
* changes:
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
feat(plat/rcar3): modify type for Internal function ar
Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration
* changes:
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
feat(plat/rcar3): modify type for Internal function argument
feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53
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| #
ffb725be |
| 02-Nov-2021 |
Takuya Sakata <takuya.sakata.wz@bp.renesas.com> |
feat(plat/rcar3): modify type for Internal function argument
Modify the type of the variable that stores the value for MPIDR
in the internal function from uint64_t to u_register_t.
Signed-off-by: K
feat(plat/rcar3): modify type for Internal function argument
Modify the type of the variable that stores the value for MPIDR
in the internal function from uint64_t to u_register_t.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ib5bda93d5432e0412132bddf41ead8ee3fcf9e46
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| #
d9912cf3 |
| 02-Nov-2021 |
Takuya Sakata <takuya.sakata.wz@bp.renesas.com> |
feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.
feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.
Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is
basically 0 and target bit value is changed to 1 only when CPU_OFF.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914
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| #
82bb6c2e |
| 02-Nov-2021 |
Takuya Sakata <takuya.sakata.wz@bp.renesas.com> |
fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53
Change internal function to call when updating value for WUPMSKCA57/53.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Sig
fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53
Change internal function to call when updating value for WUPMSKCA57/53.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id20e65e27861dd73a149ff487123859581a9b5c5
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| #
bf63dc56 |
| 18-Oct-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I684d54a7,I61339fc5,Ic0dabf3e,Ief09a841 into integration
* changes:
feat(plat/rcar): change process for Suspend To RAM
fix(plat/rcar): change process that copy code to system ram
Merge changes I684d54a7,I61339fc5,Ic0dabf3e,Ief09a841 into integration
* changes:
feat(plat/rcar): change process for Suspend To RAM
fix(plat/rcar): change process that copy code to system ram
fix(plat/rcar): fix cache maintenance process of reading cert header
fix(plat/rcar): fix to load image when option BL2_DCACHE_ENABLE is enabled
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| #
49593cc1 |
| 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
fix(plat/rcar): change process that copy code to system ram
Change processing of invalidate instruction cache to after changing
the RAM attribute.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.
fix(plat/rcar): change process that copy code to system ram
Change processing of invalidate instruction cache to after changing
the RAM attribute.
Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # squash with rcar_gen3: drivers: Disable data cache while Suspend To RAM
Change-Id: I61339fc5415b26074b1e0753da4c4a432e8f83d9
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| #
a6db44ad |
| 05-Oct-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration
* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
fea
Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration
* changes:
feat(plat/rcar3): keep RWDT enabled
feat(drivers/rcar3): add extra offset if booting B-side
feat(plat/rcar3): modify LifeC register setting for R-Car D3
feat(plat/rcar3): modify SWDT counter setting for R-Car D3
feat(plat/rcar3): update DDR setting for R-Car D3
feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3
feat(plat/rcar3): add process of SSCG setting for R-Car D3
feat(plat/rcar3): add process to back up X6 and X7 register's value
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up
feat(plat/rcar3): change the memory map for OP-TEE
feat(plat/rcar3): use PRR cut to determine DRAM size on M3
feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537
fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3
fix(plat/rcar3): fix eMMC boot support for R-Car D3
fix(plat/rcar3): fix version judgment for R-Car D3
fix(plat/rcar3): fix source file to make about GICv2
fix(drivers/rcar3): console: fix a return value of console_rcar_init
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| #
d10f8767 |
| 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
Modified the operation register to clearing the state bit of
the SYSCISR register from SYSCISR to SYSCISCR.
Signed-off-by: Hidey
feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
Modified the operation register to clearing the state bit of
the SYSCISR register from SYSCISR to SYSCISCR.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9a0820b6414425fa2f4197f60852137827414a4d
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| #
63a7a347 |
| 12-Jul-2021 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up
Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.
Signed-off-by: Hideyuki Nitta <hideyuki.nitt
feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up
Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b
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| #
c87f2c1d |
| 13-Aug-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
* changes:
feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
feat(plat/rcar3): add a DRAM siz
Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
* changes:
feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
feat(plat/rcar3): add a DRAM size setting for M3N
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0
feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
feat(drivers/rcar3): ddr: add function to judge a DDR rank
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
fix(drivers/rcar3): i2c_dvfs: fix I2C operation
fix(drivers/rcar3): fix CPG registers redefinition
fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition
fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0
refactor(plat/rcar3): factor out DT memory node generation
feat(plat/rcar3): add optional support for gzip-compressed BL33
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| #
0dae56bb |
| 30-Nov-2020 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
fix(drivers/rcar3): fix CPG registers redefinition
This commit deletes the value of the redefined CPG register.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by
fix(drivers/rcar3): fix CPG registers redefinition
This commit deletes the value of the redefined CPG register.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
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| #
65d227c3 |
| 14-Jan-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Ie8922309,I1001bea1,I66265e5e,I2cc0ceda,I04805d72, ... into integration
* changes:
plat: renesas: common: Include ulcb_cpld.h conditionally
plat: renesas: Move to common
plat: re
Merge changes Ie8922309,I1001bea1,I66265e5e,I2cc0ceda,I04805d72, ... into integration
* changes:
plat: renesas: common: Include ulcb_cpld.h conditionally
plat: renesas: Move to common
plat: renesas: aarch64: Move to common
drivers: renesas: Move ddr/qos/qos header files
drivers: renesas: rpc: Move to common
drivers: renesas: avs: Move to common
drivers: renesas: auth: Move to common
drivers: renesas: dma: Move to common
drivers: renesas: watchdog: Move to common
drivers: renesas: rom: Move to common
drivers: renesas: delay: Move to common
drivers: renesas: console: Move to common
drivers: renesas: pwrc: Move to common
drivers: renesas: io: Move to common
drivers: renesas: eMMC: Move to common
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| #
c40739a6 |
| 16-Dec-2020 |
Biju Das <biju.das.jz@bp.renesas.com> |
drivers: renesas: pwrc: Move to common
Move pwrc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@b
drivers: renesas: pwrc: Move to common
Move pwrc driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I75d91a44d872fe2296b15c700efacd5721385363
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