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Searched refs:CTX_GPREG_X4 (Results 1 – 13 of 13) sorted by relevance

/rk3399_ARM-atf/plat/arm/board/fvp/aarch64/
H A Dfvp_lsp_ras_sp.c87 event_num = (int)read_ctx_reg(get_gpregs_ctx(ns_cpu_context), CTX_GPREG_X4); in injected_fault_handler()
/rk3399_ARM-atf/include/arch/aarch64/
H A Dsmccc_helpers.h53 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \
114 _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dmce.c186 arg3 = read_ctx_reg(gp_regs, CTX_GPREG_X4); in mce_command_handler()
194 write_ctx_reg(gp_regs, CTX_GPREG_X4, (0ULL)); in mce_command_handler()
/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dwa_cve_2017_5715_bpiall.S28 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
292 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
H A Dneoverse_n1.S275 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
/rk3399_ARM-atf/services/std_svc/spmd/
H A Dspmd_logical_sp.c147 write_ctx_reg(gpregs, CTX_GPREG_X4, x4); in spmd_build_direct_message_req()
162 retval->arg4 = read_ctx_reg(gpregs, CTX_GPREG_X4); in spmd_encode_ctx_to_ffa_value()
203 write_ctx_reg(gpregs, CTX_GPREG_X4, 0U); in spmd_build_ffa_info_get_regs()
H A Dspmd_main.c120 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); in spmd_build_spmc_message()
196 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4, core_id); in spmd_setup_context()
272 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); in spmd_secure_interrupt_handler()
/rk3399_ARM-atf/bl31/aarch64/
H A Druntime_exceptions.S604 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
623 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
/rk3399_ARM-atf/services/spd/opteed/
H A Dopteed_main.c708 CTX_GPREG_X4, in opteed_smc_handler()
710 CTX_GPREG_X4)); in opteed_smc_handler()
/rk3399_ARM-atf/services/spd/tlkd/
H A Dtlkd_main.c331 write_ctx_reg(gp_regs, CTX_GPREG_X4, (uint32_t)x2); in tlkd_smc_handler()
/rk3399_ARM-atf/plat/qti/qtiseclib/src/
H A Dqtiseclib_cb_interface.c154 qti_ns_ctx->x4 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4); in qtiseclib_cb_get_ns_ctx()
/rk3399_ARM-atf/include/lib/el3_runtime/aarch64/
H A Dcontext.h42 #define CTX_GPREG_X4 U(0x20) macro
/rk3399_ARM-atf/lib/el3_runtime/aarch64/
H A Dcontext.S355 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
494 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]