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Searched refs:CLKMGR_MEM_WR (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_clock_manager.h71 #define CLKMGR_MEM_WR BIT(25) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_clock_manager.h149 #define CLKMGR_MEM_WR BIT(25) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.c165 val = (CLKMGR_MEM_REQ | CLKMGR_MEM_WR | in pll_source_sync_config()
184 val = ((CLKMGR_MEM_REQ & ~CLKMGR_MEM_WR) | addr); in pll_source_sync_read()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_clock_manager.c56 val = (CLKMGR_MEM_WR | CLKMGR_MEM_REQ | in pll_source_sync_config()