Searched refs:CLKMGR_MAINPLL (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_clock_manager.c | 132 req_status = mmio_read_32(CLKMGR_MAINPLL(MEM)); in pll_source_sync_wait()
144 req_status = mmio_read_32(CLKMGR_MAINPLL(MEM)); in pll_source_sync_wait()
169 mmio_write_32(CLKMGR_MAINPLL(MEM), val); in pll_source_sync_config()
187 mmio_write_32(CLKMGR_MAINPLL(MEM), val); in pll_source_sync_read()
199 *rdata = mmio_read_32(CLKMGR_MAINPLL(MEMSTAT)); in pll_source_sync_read()
231 mmio_setbits_32(CLKMGR_MAINPLL(BYPASS), CLKMGR_MAINPLL_BYPASS_ALL); in config_clkmgr_handoff()
243 mmio_clrbits_32(CLKMGR_MAINPLL(PLLGLOB), in config_clkmgr_handoff()
251 mmio_write_32(CLKMGR_MAINPLL(PLLGLOB), in config_clkmgr_handoff()
253 mmio_write_32(CLKMGR_MAINPLL(FDBCK), hoff_ptr->main_pll_fdbck); in config_clkmgr_handoff()
254 mmio_write_32(CLKMGR_MAINPLL(VCOCALIB), mainpll_vcocalib); in config_clkmgr_handoff()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/agilex/soc/ |
| H A D | agilex_clock_manager.c | 104 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_BYPASS, 0x7); in config_clkmgr_handoff()
112 mmio_clrbits_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB, in config_clkmgr_handoff()
132 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLGLOB, in config_clkmgr_handoff()
135 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_FDBCK, in config_clkmgr_handoff()
137 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_VCOCALIB, in config_clkmgr_handoff()
140 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC0, in config_clkmgr_handoff()
142 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC1, in config_clkmgr_handoff()
144 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC2, in config_clkmgr_handoff()
146 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLC3, in config_clkmgr_handoff()
148 mmio_write_32(CLKMGR_MAINPLL + CLKMGR_MAINPLL_PLLM, in config_clkmgr_handoff()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | agilex_clock_manager.h | 20 #define CLKMGR_MAINPLL 0xffd10024 macro
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | agilex5_clock_manager.h | 60 #define CLKMGR_MAINPLL(_reg) (CLKMGR_MAINPLL_BASE + \ macro
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