Home
last modified time | relevance | path

Searched refs:AXI_DCMPAREACRA0 (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/renesas/common/include/registers/
H A Daxi_registers.h34 #define AXI_DCMPAREACRA0 (AXI_BASE + 0x4100U) macro
/rk3399_ARM-atf/plat/renesas/rzg/
H A Dbl2_plat_setup.c218 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg); in bl2_lossy_setting()
220 mmio_write_32(AXI_DCMPAREACRA0 + 0x8U * no, reg | enable); in bl2_lossy_setting()
223 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no); in bl2_lossy_setting()
231 mmio_read_32(AXI_DCMPAREACRA0 + 0x8U * no), in bl2_lossy_setting()
/rk3399_ARM-atf/plat/renesas/rcar/
H A Dbl2_plat_setup.c220 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); in bl2_lossy_setting()
222 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable); in bl2_lossy_setting()
225 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); in bl2_lossy_setting()
233 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), in bl2_lossy_setting()
/rk3399_ARM-atf/plat/renesas/common/include/
H A Drcar_def.h293 #define AXI_DCMPAREACRA0 (0xE6784100U) macro