Home
last modified time | relevance | path

Searched refs:APU_ACC_CONFG_CLR0 (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl.c40 APU_ACC_CONFG_CLR0, APU_ACC_CONFG_CLR7
50 { APU_ACC_CONFG_CLR0, BIT(BIT_CGEN_SOC) },
H A Dapupwr_clkctl_def.h165 #define APU_ACC_CONFG_CLR0 (APU_ACC_BASE + 0x040) macro
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_power.h104 #define APU_ACC_CONFG_CLR0 (0x010) macro
H A Dapusys_power.c135 apu_w_are(are_idx++, base_reg + APU_ACC_CONFG_CLR0, CGEN_SOC); in apu_acc_init()
147 apu_w_are(are_idx++, base_reg + APU_ACC_CONFG_CLR0, CGEN_SOC); in apu_acc_init()
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/
H A Dapusys_power.h134 #define APU_ACC_CONFG_CLR0 (0x0040) macro
H A Dapusys_power.c314 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_CLR0, CGEN_SOC); in apu_acc_init()