Searched refs:AGX5_PWRMGR (Results 1 – 4 of 4) sorted by relevance
215 boot_core = ((mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00) >> 10); in bl31_plat_arch_setup()266 boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00); in bl31_plat_set_secondary_cpu_entrypoint()285 pchctlr_old = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); in bl31_plat_set_secondary_cpu_entrypoint()287 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pchctlr_new); in bl31_plat_set_secondary_cpu_entrypoint()306 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR0); in bl31_plat_reset_secondary_cpu()307 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT0); in bl31_plat_reset_secondary_cpu()310 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR1); in bl31_plat_reset_secondary_cpu()311 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT1); in bl31_plat_reset_secondary_cpu()314 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR2); in bl31_plat_reset_secondary_cpu()315 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT2); in bl31_plat_reset_secondary_cpu()[all …]
25 data = mmio_read_32(AGX5_PWRMGR(PSS_PGSTAT)); in wait_verify_fsm()34 pgstat = mmio_read_32(AGX5_PWRMGR(PSS_PGSTAT)); in wait_verify_fsm()51 mmio_write_32(AGX5_PWRMGR(PSS_FWENCTL), in pss_sram_power_off()58 mmio_write_32(AGX5_PWRMGR(PSS_PGENCTL), in pss_sram_power_off()
82 #define AGX5_PWRMGR(_reg) (AGX5_PWRMGR_BASE + \ macro
82 pch_cpu = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)) & in socfpga_pwr_domain_on()