Lines Matching refs:AGX5_PWRMGR
215 boot_core = ((mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00) >> 10); in bl31_plat_arch_setup()
266 boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00); in bl31_plat_set_secondary_cpu_entrypoint()
285 pchctlr_old = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); in bl31_plat_set_secondary_cpu_entrypoint()
287 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pchctlr_new); in bl31_plat_set_secondary_cpu_entrypoint()
306 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR0); in bl31_plat_reset_secondary_cpu()
307 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT0); in bl31_plat_reset_secondary_cpu()
310 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR1); in bl31_plat_reset_secondary_cpu()
311 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT1); in bl31_plat_reset_secondary_cpu()
314 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR2); in bl31_plat_reset_secondary_cpu()
315 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT2); in bl31_plat_reset_secondary_cpu()
318 pwrctlr_addr = AGX5_PWRMGR(CPU_PWRCTLR3); in bl31_plat_reset_secondary_cpu()
319 pwrstat_addr = AGX5_PWRMGR(CPU_PWRSTAT3); in bl31_plat_reset_secondary_cpu()
370 pch_cpu = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR)); in bl31_plat_set_secondary_cpu_off()
373 mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu); in bl31_plat_set_secondary_cpu_off()