| /optee_os/core/arch/arm/plat-rockchip/ |
| H A D | psci_rk322x.c | 66 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE, CRU_SIZE); in clks_disable() local
69 dram_d.cru_clkgate[i] = io_read32(va_base + CRU_CLKGATE_CON(i)); in clks_disable()
70 io_write32(va_base + CRU_CLKGATE_CON(i), in clks_disable()
78 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE, CRU_SIZE); in clks_restore() local
81 io_write32(va_base + CRU_CLKGATE_CON(i), in clks_restore()
87 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE, CRU_SIZE); in pll_power_down() local
89 io_write32(va_base + CRU_MODE_CON, PLL_SLOW_MODE(pll)); in pll_power_down()
90 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_DOWN); in pll_power_down()
95 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE, CRU_SIZE); in pll_power_up() local
97 io_write32(va_base + CRU_PLL_CON1(pll), PLL_POWER_UP); in pll_power_up()
[all …]
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| /optee_os/core/arch/riscv/mm/ |
| H A D | core_mmu_arch.c | 271 vaddr_t va_base = SHIFT_U64(idx, CORE_MMU_SHIFT_OF_LEVEL(level)); in core_mmu_pgt_get_va_base()
275 if (va_base & va_width_msb) in core_mmu_pgt_get_va_base()
276 return va_extended_mask | va_base; in core_mmu_pgt_get_va_base()
278 return va_base; in core_mmu_pgt_get_va_base()
760 vaddr_t va_base = 0; in core_mmu_find_table() local
772 idx = core_mmu_pgt_idx(va - va_base, level); in core_mmu_find_table()
777 core_mmu_set_info_table(tbl_info, level, va_base, pgt); in core_mmu_find_table()
784 va_base += core_mmu_pgt_get_va_base(level, idx); in core_mmu_find_table()
825 unsigned int level, vaddr_t va_base, void *table) in core_mmu_set_info_table() argument
830 tbl_info->va_base = va_base; in core_mmu_set_info_table()
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| /optee_os/core/include/mm/ |
| H A D | core_mmu.h | 410 vaddr_t va_base; member
484 return (va - tbl_info->va_base) >> tbl_info->shift; in core_mmu_va2idx()
496 return (idx << tbl_info->shift) + tbl_info->va_base; in core_mmu_idx2va()
681 unsigned int level, vaddr_t va_base, void *table);
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| /optee_os/core/pta/tests/ |
| H A D | misc.c | 619 vaddr_t va_base = VCORE_FREE_PA; in self_test_va2pa() local
622 pa_base = virt_to_phys((void *)va_base); in self_test_va2pa()
624 LOG("virt_to_phys(%#"PRIxVA") => 0 Fail!", va_base); in self_test_va2pa()
637 if (check_virt_to_phys(va_base, pa_base, MEM_AREA_TEE_RAM)) in self_test_va2pa()
639 if (check_virt_to_phys(va_base + 16, pa_base + 16, in self_test_va2pa()
642 if (check_virt_to_phys(va_base + VCORE_FREE_SZ - in self_test_va2pa()
645 if (check_virt_to_phys(va_base + VCORE_FREE_SZ - 16, 0, in self_test_va2pa()
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| /optee_os/core/arch/arm/mm/ |
| H A D | core_mmu_lpae.c | 1231 unsigned level, vaddr_t va_base, void *table) in core_mmu_set_info_table() argument
1236 tbl_info->va_base = va_base; in core_mmu_set_info_table()
1280 vaddr_t va_base = 0; in core_mmu_find_table() local
1290 unsigned int n = (va - va_base) >> level_size_shift; in core_mmu_find_table()
1313 tbl_info->va_base = va_base; in core_mmu_find_table()
1330 va_base += (vaddr_t)n << level_size_shift; in core_mmu_find_table()
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| H A D | core_mmu_v7.c | 540 unsigned level, vaddr_t va_base, void *table) in core_mmu_set_info_table() argument
545 tbl_info->va_base = va_base; in core_mmu_set_info_table()
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| H A D | tee_pager.c | 339 n = ((va & ~mask) - pager_tables[0].tbl_info.va_base) >> in find_pager_table_may_fail()
344 assert(va >= pager_tables[n].tbl_info.va_base && in find_pager_table_may_fail()
345 va <= (pager_tables[n].tbl_info.va_base | mask)); in find_pager_table_may_fail()
557 pager_tables[n].pgt.vabase = pager_tables[n].tbl_info.va_base; in tee_pager_early_init()
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| /optee_os/core/mm/ |
| H A D | vm.c | 185 vaddr_t va = MAX(r->va, ti->va_base); in set_reg_in_table()
186 vaddr_t end = MIN(r->va + r->size, ti->va_base + CORE_MMU_PGDIR_SIZE); in set_reg_in_table()
213 ti.va_base = p->vabase; in set_um_region()
223 for (ti.va_base = ROUNDDOWN(r->va, CORE_MMU_PGDIR_SIZE); in set_um_region()
224 ti.va_base < r->va + r->size; in set_um_region()
225 ti.va_base += CORE_MMU_PGDIR_SIZE) { in set_um_region()
226 p = pgt_pop_from_cache_list(ti.va_base, uctx->ts_ctx); in set_um_region()
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| H A D | core_mmu.c | 965 va = tbl_info.va_base; in dump_xlat_table()
1888 r.va >= (pg_info->va_base + CORE_MMU_PGDIR_SIZE)) { in set_pg_region()
1895 assert(r.va > pg_info->va_base); in set_pg_region()
1898 pg_info->va_base = core_mmu_idx2va(dir_info, idx); in set_pg_region()
1905 while ((*pgt)->vabase < pg_info->va_base) { in set_pg_region()
1910 assert((*pgt)->vabase == pg_info->va_base); in set_pg_region()
1918 r.size = MIN(CORE_MMU_PGDIR_SIZE - (r.va - pg_info->va_base), in set_pg_region()
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