Searched refs:pllcfg (Results 1 – 2 of 2) sorted by relevance
1410 uint32_t *pllcfg, in clk_stm32_pll_config_output() argument1453 assert(pllcfg[REFDIV]); in clk_stm32_pll_config_output()1456 SHIFT_U32(pllcfg[FBDIV], RCC_PLLxCFGR2_FBDIV_SHIFT) & in clk_stm32_pll_config_output()1459 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK); in clk_stm32_pll_config_output()1461 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); in clk_stm32_pll_config_output()1463 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); in clk_stm32_pll_config_output()1465 if (!pllcfg[POSTDIV1] || !pllcfg[POSTDIV2]) { in clk_stm32_pll_config_output()
1428 uint32_t *pllcfg, in clk_stm32_pll_config_output() argument1471 assert(pllcfg[REFDIV]); in clk_stm32_pll_config_output()1474 SHIFT_U32(pllcfg[FBDIV], RCC_PLLxCFGR2_FBDIV_SHIFT) & in clk_stm32_pll_config_output()1477 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK); in clk_stm32_pll_config_output()1479 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); in clk_stm32_pll_config_output()1481 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); in clk_stm32_pll_config_output()1483 if (!pllcfg[POSTDIV1] || !pllcfg[POSTDIV2]) { in clk_stm32_pll_config_output()