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Searched refs:io_mask32 (Results 1 – 10 of 10) sorted by relevance

/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
H A Dhal_ctrl.c42 io_mask32(baseaddr + MCFGR, MCFGR_AXIPIPE(1), BM_MCFGR_AXIPIPE); in caam_hal_ctrl_init()
/optee_os/core/drivers/
H A Dstm32_shared_io.c27 io_mask32(va, value, mask); in io_mask32_stm32shregs()
H A Dimx_csu.c99 io_mask32(csu_base + csu_index * 4, 0x330000, 0xFF0000); in rngb_configure()
H A Dstm32_bsec.c224 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP_MASK, in power_up_safmem()
242 io_mask32(bsec_base() + BSEC_OTP_CONF_OFF, 0, BSEC_CONF_POWER_UP_MASK); in power_down_safmem()
H A Dstm32_exti.c180 io_mask32(exti->base + _EXTI_RTSR(i), r_trig, mask); in stm32_exti_set_type()
181 io_mask32(exti->base + _EXTI_FTSR(i), f_trig, mask); in stm32_exti_set_type()
H A Dstm32_gpio.c1011 io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET, in apply_rif_config()
1013 io_mask32(bank->base + GPIO_SECR_OFFSET, in apply_rif_config()
H A Dgic.c718 io_mask32(gd->gicd_base + GICD_ICFGR(index), in gic_it_set_type()
/optee_os/core/arch/arm/plat-rzn1/
H A Dsm_platform_handler.c56 io_mask32(reg, *pvalue, mask); in oem_sysreg()
/optee_os/core/drivers/crypto/caam/hal/common/
H A Dhal_jr.c148 io_mask32(baseaddr + JRX_JRCFGR_LS, ~JRX_JRCFGR_LS_IMSK, in caam_hal_jr_enable_itr()
/optee_os/core/include/
H A Dio.h75 static inline void io_mask32(vaddr_t addr, uint32_t val, uint32_t mask) in io_mask32() function