Home
last modified time | relevance | path

Searched refs:fbdiv (Results 1 – 2 of 2) sorted by relevance

/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c1390 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, in stm32mp2_a35_pll1_config() argument
1396 SHIFT_U32(fbdiv, CA35SS_SSC_PLL_FREQ1_FBDIV_SHIFT), in stm32mp2_a35_pll1_config()
2074 uint32_t fbdiv = 0; in clk_get_pll1_fvco_rate() local
2078 fbdiv = (reg & CA35SS_SSC_PLL_FREQ1_FBDIV_MASK) >> in clk_get_pll1_fvco_rate()
2084 if (!refdiv || MUL_OVERFLOW(refclk, fbdiv, &freq)) in clk_get_pll1_fvco_rate()
2166 uint32_t fbdiv = 0; in clk_get_pll_fvco() local
2170 fbdiv = (io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >> in clk_get_pll_fvco()
2181 numerator = SHIFT_U64(fbdiv, 24) + fracin; in clk_get_pll_fvco()
2186 fvco = (unsigned long)(prate * fbdiv / refdiv); in clk_get_pll_fvco()
H A Dclk-stm32mp25.c1408 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, in stm32mp2_a35_pll1_config() argument
1414 SHIFT_U32(fbdiv, CA35SS_SSC_PLL_FREQ1_FBDIV_SHIFT), in stm32mp2_a35_pll1_config()
2067 uint32_t fbdiv = 0; in clk_get_pll1_fvco_rate() local
2071 fbdiv = (reg & CA35SS_SSC_PLL_FREQ1_FBDIV_MASK) >> in clk_get_pll1_fvco_rate()
2077 if (!refdiv || MUL_OVERFLOW(refclk, fbdiv, &freq)) in clk_get_pll1_fvco_rate()
2159 uint32_t fbdiv = 0; in clk_get_pll_fvco() local
2163 fbdiv = (io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >> in clk_get_pll_fvco()
2174 numerator = SHIFT_U64(fbdiv, 24) + fracin; in clk_get_pll_fvco()
2179 fvco = (unsigned long)(prate * fbdiv / refdiv); in clk_get_pll_fvco()