Home
last modified time | relevance | path

Searched refs:baseaddr (Results 1 – 20 of 20) sorted by relevance

/optee_os/core/drivers/crypto/caam/hal/common/
H A Dhal_jr.c29 enum caam_status caam_hal_jr_reset(vaddr_t baseaddr) in caam_hal_jr_reset() argument
41 io_setbits32(baseaddr + JRX_JRCFGR_LS, JRX_JRCFGR_LS_IMSK); in caam_hal_jr_reset()
44 io_caam_write32(baseaddr + JRX_JRCR, JRX_JRCR_RESET); in caam_hal_jr_reset()
48 reg_val = io_caam_read32(baseaddr + JRX_JRINTR); in caam_hal_jr_reset()
59 io_caam_write32(baseaddr + JRX_JRCR, JRX_JRCR_RESET); in caam_hal_jr_reset()
62 reg_val = io_caam_read32(baseaddr + JRX_JRCR); in caam_hal_jr_reset()
73 void caam_hal_jr_config(vaddr_t baseaddr, uint8_t nbjobs, uint64_t inrings, in caam_hal_jr_config() argument
80 io_caam_write32(baseaddr + JRX_IRBAR, inrings); in caam_hal_jr_config()
81 io_caam_write32(baseaddr + JRX_IRBAR + 4, inrings >> 32); in caam_hal_jr_config()
83 io_caam_write32(baseaddr + JRX_IRBAR, inrings >> 32); in caam_hal_jr_config()
[all …]
H A Dhal_rng.c15 enum caam_status __weak caam_hal_rng_instantiated(vaddr_t baseaddr) in caam_hal_rng_instantiated() argument
22 if (caam_hal_ctrl_era(baseaddr) < 10) { in caam_hal_rng_instantiated()
23 vid = io_caam_read32(baseaddr + CHAVID_LS); in caam_hal_rng_instantiated()
28 vid = io_caam_read32(baseaddr + RNG_VERSION); in caam_hal_rng_instantiated()
35 nb_sh = caam_hal_rng_get_nb_sh(baseaddr); in caam_hal_rng_instantiated()
38 status = caam_hal_rng_get_sh_status(baseaddr); in caam_hal_rng_instantiated()
46 uint32_t caam_hal_rng_get_nb_sh(vaddr_t baseaddr) in caam_hal_rng_get_nb_sh() argument
50 reg = io_caam_read32(baseaddr + CTPR_MS); in caam_hal_rng_get_nb_sh()
55 uint32_t caam_hal_rng_get_sh_status(vaddr_t baseaddr) in caam_hal_rng_get_sh_status() argument
57 return io_caam_read32(baseaddr + RNG_STA) & (RNG_STA_IF1 | RNG_STA_IF0); in caam_hal_rng_get_sh_status()
[all …]
H A Dhal_ctrl.c19 uint8_t caam_hal_ctrl_era(vaddr_t baseaddr) in caam_hal_ctrl_era() argument
22 uint32_t val = io_caam_read32(baseaddr + CCBVID); in caam_hal_ctrl_era()
27 uint8_t caam_hal_ctrl_jrnum(vaddr_t baseaddr) in caam_hal_ctrl_jrnum() argument
32 if (caam_hal_ctrl_era(baseaddr) < 10) { in caam_hal_ctrl_jrnum()
33 val = io_caam_read32(baseaddr + CHANUM_MS); in caam_hal_ctrl_jrnum()
36 val = io_caam_read32(baseaddr + JR_VERSION); in caam_hal_ctrl_jrnum()
43 uint8_t caam_hal_ctrl_hash_limit(vaddr_t baseaddr) in caam_hal_ctrl_hash_limit() argument
47 if (caam_hal_ctrl_era(baseaddr) < 10) { in caam_hal_ctrl_hash_limit()
49 val = io_caam_read32(baseaddr + CHANUM_LS); in caam_hal_ctrl_hash_limit()
53 val = io_caam_read32(baseaddr + CHAVID_LS); in caam_hal_ctrl_hash_limit()
[all …]
/optee_os/core/drivers/crypto/caam/include/
H A Dcaam_hal_jr.h31 enum caam_status caam_hal_jr_reset(vaddr_t baseaddr);
41 void caam_hal_jr_config(vaddr_t baseaddr, uint8_t nbjobs, uint64_t inrings,
49 uint32_t caam_hal_jr_read_nbslot_available(vaddr_t baseaddr);
56 void caam_hal_jr_add_newjob(vaddr_t baseaddr);
63 uint32_t caam_hal_jr_get_nbjob_done(vaddr_t baseaddr);
70 void caam_hal_jr_del_job(vaddr_t baseaddr);
77 void caam_hal_jr_disable_itr(vaddr_t baseaddr);
84 void caam_hal_jr_enable_itr(vaddr_t baseaddr);
91 bool caam_hal_jr_check_ack_itr(vaddr_t baseaddr);
99 enum caam_status caam_hal_jr_halt(vaddr_t baseaddr);
[all …]
H A Dcaam_hal_rng.h19 enum caam_status caam_hal_rng_instantiated(vaddr_t baseaddr);
26 uint32_t caam_hal_rng_get_nb_sh(vaddr_t baseaddr);
33 uint32_t caam_hal_rng_get_sh_status(vaddr_t baseaddr);
40 bool caam_hal_rng_key_loaded(vaddr_t baseaddr);
47 bool caam_hal_rng_pr_enabled(vaddr_t baseaddr);
55 enum caam_status caam_hal_rng_kick(vaddr_t baseaddr, uint32_t inc_delay);
H A Dcaam_hal_ctrl.h18 void caam_hal_ctrl_init(vaddr_t baseaddr);
25 uint8_t caam_hal_ctrl_jrnum(vaddr_t baseaddr);
33 uint8_t caam_hal_ctrl_hash_limit(vaddr_t baseaddr);
40 uint8_t caam_hal_ctrl_pknum(vaddr_t baseaddr);
47 bool caam_hal_ctrl_splitkey_support(vaddr_t baseaddr);
54 uint8_t caam_hal_ctrl_era(vaddr_t baseaddr);
61 void caam_hal_ctrl_inc_priblob(vaddr_t baseaddr);
H A Dcaam_blob.h16 enum caam_status caam_blob_mkvb_init(vaddr_t baseaddr);
18 static inline enum caam_status caam_blob_mkvb_init(vaddr_t baseaddr __unused) in caam_blob_mkvb_init()
H A Dcaam_pwr.h34 vaddr_t baseaddr; /* Register virtual base address */ member
49 void caam_pwr_add_backup(vaddr_t baseaddr, const struct reglist *regs,
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
H A Dhal_ctrl.c26 void caam_hal_ctrl_init(vaddr_t baseaddr) in caam_hal_ctrl_init() argument
29 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
42 io_mask32(baseaddr + MCFGR, MCFGR_AXIPIPE(1), BM_MCFGR_AXIPIPE); in caam_hal_ctrl_init()
44 caam_pwr_add_backup(baseaddr, ctrl_backup, ARRAY_SIZE(ctrl_backup)); in caam_hal_ctrl_init()
/optee_os/core/drivers/crypto/caam/
H A Dcaam_jr.c43 vaddr_t baseaddr; /* Job Ring base address */ member
193 nb_jobs_done = caam_hal_jr_get_nbjob_done(jr_privdata->baseaddr); in do_jr_dequeue()
264 caam_hal_jr_del_job(jr_privdata->baseaddr); in do_jr_dequeue()
310 while (caam_hal_jr_read_nbslot_available(jr_privdata->baseaddr) == 0) { in do_jr_enqueue()
377 caam_hal_jr_add_newjob(jr_privdata->baseaddr); in do_jr_enqueue()
439 it_active = caam_hal_jr_check_ack_itr(jr_privdata->baseaddr); in caam_jr_dequeue()
559 jr_privdata->baseaddr = jrcfg->base + jrcfg->offset; in caam_jr_init()
560 retstatus = caam_hal_jr_reset(jr_privdata->baseaddr); in caam_jr_init()
577 caam_hal_jr_config(jr_privdata->baseaddr, jr_privdata->nb_jobs, in caam_jr_init()
597 caam_hal_jr_enable_itr(jr_privdata->baseaddr); in caam_jr_init()
[all …]
H A Dcaam_pwr.c22 void caam_pwr_add_backup(vaddr_t baseaddr, const struct reglist *regs, in caam_pwr_add_backup() argument
38 newelem->baseaddr = baseaddr; in caam_pwr_add_backup()
74 io_caam_read32(elem->baseaddr + in do_save_regs()
80 elem->baseaddr + reg->offset + in do_save_regs()
104 elem->baseaddr + reg->offset + in do_restore_regs()
107 io_caam_write32(elem->baseaddr + reg->offset + in do_restore_regs()
H A Dcaam_rng.c32 vaddr_t baseaddr; /* RNG base address */ member
154 key_loaded = caam_hal_rng_key_loaded(rng_privdata->baseaddr); in prepare_inst_desc()
219 retstatus = caam_hal_rng_instantiated(rng_privdata->baseaddr); in caam_rng_instantiation()
231 nb_sh = caam_hal_rng_get_nb_sh(rng_privdata->baseaddr); in caam_rng_instantiation()
268 sh_status = caam_hal_rng_get_sh_status(rng_privdata->baseaddr); in caam_rng_instantiation()
278 retstatus = caam_hal_rng_kick(rng_privdata->baseaddr, in caam_rng_instantiation()
313 caam_hal_rng_pr_enabled(rng_privdata->baseaddr) & in caam_rng_instantiation()
334 rng_privdata->baseaddr = ctrl_addr; in caam_rng_init()
H A Dcaam_sm.c17 vaddr_t baseaddr; /* Secure memory base address */ member
68 page_addr->vaddr = sm_privdata.baseaddr + in caam_sm_alloc()
176 sm_privdata.baseaddr = caam_hal_sm_get_base(); in caam_sm_init()
178 if (!sm_privdata.baseaddr) in caam_sm_init()
182 sm_privdata.baseaddr); in caam_sm_init()
/optee_os/core/drivers/crypto/caam/hal/imx_8m/
H A Dhal_ctrl.c12 void caam_hal_ctrl_init(vaddr_t baseaddr) in caam_hal_ctrl_init() argument
15 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/
H A Dhal_ctrl.c13 void caam_hal_ctrl_init(vaddr_t baseaddr) in caam_hal_ctrl_init() argument
16 io_setbits32(baseaddr + MCFGR, MCFGR_WDE); in caam_hal_ctrl_init()
/optee_os/core/drivers/crypto/caam/hal/imx_8q/
H A Dhal_rng.c11 enum caam_status caam_hal_rng_instantiated(vaddr_t baseaddr __unused) in caam_hal_rng_instantiated()
22 bool caam_hal_rng_pr_enabled(vaddr_t baseaddr __unused) in caam_hal_rng_pr_enabled()
H A Dhal_ctrl.c8 void caam_hal_ctrl_init(vaddr_t baseaddr __unused) in caam_hal_ctrl_init()
/optee_os/core/drivers/crypto/caam/blob/
H A Dcaam_blob.c23 enum caam_status caam_blob_mkvb_init(vaddr_t baseaddr) in caam_blob_mkvb_init() argument
68 caam_hal_ctrl_inc_priblob(baseaddr); in caam_blob_mkvb_init()
/optee_os/core/drivers/crypto/caam/hal/ls/
H A Dhal_ctrl.c11 void caam_hal_ctrl_init(vaddr_t baseaddr __unused) in caam_hal_ctrl_init()
/optee_os/core/drivers/
H A Dbcm_gpio.c163 vaddr_t baseaddr = in iproc_gpio_set_secure() local
169 regaddr = baseaddr + IPROC_GPIO_SEC_CFG_REG(gpiopin); in iproc_gpio_set_secure()