xref: /optee_os/core/drivers/amd/asu/asu_doorbell.h (revision 7f2d4e10736f698f6b7739a9cd39e64d96c98a0a)
1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (c) 2024-2026, Advanced Micro Devices, Inc. All Rights Reserved.
4  *
5  */
6 
7 #ifndef __ASU_DOORBELL_H__
8 #define __ASU_DOORBELL_H__
9 
10 #include <stdint.h>
11 
12 #define PAR_IPIPSU_NUM_INSTANCES	1U
13 
14 /* Parameter definitions for peripheral ASU IPI */
15 #define PAR_IPIPSU_0_DEVICE_ID		0U
16 #define PAR_IPIPSU_0_BASEADDR		0xEB330000U
17 #define PAR_IPIPSU_0_BIT_MASK		0x00000001U
18 #define PAR_IPIPSU_0_INT_ID		0x59U
19 #define PAR_IPIPSU_NUM_TARGETS		16U
20 #define PAR_PSV_IPI_PMC_BIT_MASK	0x2U
21 #define PAR_PSV_IPI_0_BIT_MASK		0x4U
22 #define PAR_PSV_IPI_1_BIT_MASK		0x8U
23 #define PAR_PSV_IPI_2_BIT_MASK		0x10U
24 #define PAR_PSV_IPI_3_BIT_MASK		0x20U
25 #define PAR_PSV_IPI_4_BIT_MASK		0x40U
26 #define PAR_PSV_IPI_5_BIT_MASK		0x80U
27 #define PAR_PSV_IPI_PMC_NOBUF_BIT_MASK	0x100U
28 #define PAR_PSV_IPI_6_BIT_MASK		0x200U
29 #define IPIPSU_ALL_MASK			0xFFFFU
30 
31 #define IPIPSU_TRIG_OFFSET	0x00U
32 #define IPIPSU_OBS_OFFSET	0x04U
33 #define IPIPSU_ISR_OFFSET	0x10U
34 #define IPIPSU_IMR_OFFSET	0x14U
35 #define IPIPSU_IER_OFFSET	0x18U
36 
37 struct asu_doorbell_config {
38 	uint32_t deviceid;
39 	uintptr_t baseaddr;
40 	uint32_t bitmask;
41 	uint32_t intrid;
42 	uintptr_t intrparent;
43 	uint32_t target_count;
44 	uint32_t target_mask[PAR_IPIPSU_NUM_TARGETS];
45 };
46 
47 struct asu_doorbell_config asu_configtable = {
48 	.deviceid = PAR_IPIPSU_0_DEVICE_ID,
49 	.baseaddr = PAR_IPIPSU_0_BASEADDR,
50 	.bitmask = PAR_IPIPSU_0_BIT_MASK,
51 	.intrid = PAR_IPIPSU_0_INT_ID,
52 	.target_count = PAR_IPIPSU_NUM_TARGETS,
53 	.target_mask = {
54 		PAR_PSV_IPI_PMC_BIT_MASK,
55 		PAR_PSV_IPI_0_BIT_MASK,
56 		PAR_PSV_IPI_1_BIT_MASK,
57 		PAR_PSV_IPI_2_BIT_MASK,
58 		PAR_PSV_IPI_3_BIT_MASK,
59 		PAR_PSV_IPI_4_BIT_MASK,
60 		PAR_PSV_IPI_5_BIT_MASK,
61 		PAR_PSV_IPI_PMC_NOBUF_BIT_MASK,
62 		PAR_PSV_IPI_6_BIT_MASK,
63 	}
64 };
65 
66 #endif /* __ASU_DOORBELL_H__ */
67