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Searched refs:RCC_PLLxCFGR6_POSTDIV1_MASK (Results 1 – 4 of 4) sorted by relevance

/optee_os/core/drivers/clk/
H A Dclk-stm32mp21.c1460 io_clrsetbits32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, in clk_stm32_pll_config_output()
1461 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); in clk_stm32_pll_config_output()
2205 postdiv1 = io_read32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK; in clk_stm32_pll_get_rate()
H A Dclk-stm32mp25.c1478 io_clrsetbits32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, in clk_stm32_pll_config_output()
1479 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); in clk_stm32_pll_config_output()
2198 postdiv1 = io_read32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK; in clk_stm32_pll_get_rate()
/optee_os/core/include/drivers/
H A Dstm32mp21_rcc.h1202 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) macro
H A Dstm32mp25_rcc.h1535 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) macro