Home
last modified time | relevance | path

Searched refs:RCC_PLLNCFGR1_DIVN_MASK (Results 1 – 4 of 4) sorted by relevance

/optee_os/core/include/drivers/
H A Dstm32mp1_rcc.h321 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK_32(8, 0) macro
H A Dstm32mp13_rcc.h1764 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK_32(8, 0) macro
/optee_os/core/drivers/clk/
H A Dclk-stm32mp15.c688 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_pll_get_fvco()
H A Dclk-stm32mp13.c1100 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_compute_cfgr1()
1728 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_get_rate()