Searched refs:RCC_FINDIV0CFGR_FINDIV0_MASK (Results 1 – 4 of 4) sorted by relevance
1681 #define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) macro1686 #define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) macro
2231 #define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) macro2236 #define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) macro
1746 RCC_FINDIV0CFGR_FINDIV0_MASK, in flexclkgen_config_channel()2293 RCC_FINDIV0CFGR_FINDIV0_MASK; in clk_stm32_flexgen_get_rate()2401 RCC_FINDIV0CFGR_FINDIV0_MASK, in clk_stm32_flexgen_set_rate()
1750 RCC_FINDIV0CFGR_FINDIV0_MASK, in flexclkgen_config_channel()2323 RCC_FINDIV0CFGR_FINDIV0_MASK; in clk_stm32_flexgen_get_rate()2426 RCC_FINDIV0CFGR_FINDIV0_MASK, in clk_stm32_flexgen_set_rate()