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Searched refs:PRIu32 (Results 1 – 25 of 70) sorted by relevance

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/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/
H A Dhal_jr.c35 HAL_TRACE("JR%" PRIu32 "DID_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
58 HAL_TRACE("JR%" PRIu32 "DID_MS value 0x%" PRIx32 " (0x%" PRIx32 in caam_hal_jr_setowner()
64 HAL_TRACE("JR%" PRIu32 "DID_LS value 0x%" PRIx32 in caam_hal_jr_setowner()
71 HAL_TRACE("JR%" PRIu32 "DID_LS set value 0x%" PRIx32, jr_idx, in caam_hal_jr_setowner()
73 HAL_TRACE("JR%" PRIu32 "DID_MS set value 0x%" PRIx32, jr_idx, in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/hal/imx_8m/
H A Dhal_jr.c34 HAL_TRACE("JR%" PRIu32 "DID_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
57 HAL_TRACE("JR%" PRIu32 "DID_MS value 0x%" PRIx32 " (0x%" PRIx32 in caam_hal_jr_setowner()
63 HAL_TRACE("JR%" PRIu32 "DID_LS value 0x%" PRIx32 in caam_hal_jr_setowner()
70 HAL_TRACE("JR%" PRIu32 "DID_LS set value 0x%" PRIx32, jr_idx, in caam_hal_jr_setowner()
72 HAL_TRACE("JR%" PRIu32 "DID_MS set value 0x%" PRIx32, jr_idx, in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
H A Dhal_jr.c34 HAL_TRACE("JR%" PRIu32 "MIDR_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
58 HAL_TRACE("JR%" PRIu32 "MIDR_MS value 0x%" PRIx32 " (0x%" PRIx32 in caam_hal_jr_setowner()
67 HAL_TRACE("JR%" PRIu32 "MIDR_LS value 0x%" PRIx32 in caam_hal_jr_setowner()
74 HAL_TRACE("JR%" PRIu32 "MIDR_LS set value 0x%" PRIx32, jr_idx, in caam_hal_jr_setowner()
76 HAL_TRACE("JR%" PRIu32 "MIDR_MS set value 0x%" PRIx32, jr_idx, in caam_hal_jr_setowner()
/optee_os/core/arch/riscv/kernel/
H A Dboot.c95 DMSG("Bringing up secondary hart%"PRIu32, hartid); in start_secondary_cores()
99 EMSG("Error starting secondary hart%"PRIu32, hartid); in start_secondary_cores()
238 IMSG("Primary CPU0 (hart%"PRIu32") initializing", in boot_init_primary_runtime()
256 IMSG("Primary CPU0 (hart%"PRIu32") initialized", in boot_init_primary_final()
268 IMSG("Secondary CPU%zu (hart%"PRIu32") initializing", in init_secondary_helper()
283 IMSG("Secondary CPU%zu (hart%"PRIu32") initialized", in init_secondary_helper()
/optee_os/core/arch/arm/plat-k3/
H A Dmain.c93 IMSG("Secure Board Configuration Software: Rev %"PRIu32, in secure_boot_information()
97 IMSG("Secure Boot Keys: Count %"PRIu32 ", Rev %"PRIu32, in secure_boot_information()
/optee_os/core/drivers/
H A Dls_sfp.c161 DMSG("Set GPIO %"PRIu32" pin %"PRIu32" to HIGH", in ls_sfp_program_fuses()
188 DMSG("Set GPIO %"PRIu8" pin %"PRIu32" to LOW", in ls_sfp_program_fuses()
289 DMSG("Index greater or equal to ouid: %"PRIu32" >= %zu", in ls_sfp_get_ouid()
326 DMSG("Index greater or equal to srkhr: %"PRIu32" >= %zu", in ls_sfp_get_srkh()
388 DMSG("Index greater or equal to ouid: %"PRIu32" >= %"PRIu32, in ls_sfp_set_ouid()
H A Datmel_piobu.c274 EMSG("Date of tampering: %02"PRIu32"/%02"PRIu32"/%02"PRIu32"", in secumod_it_handler()
276 EMSG("Time of tampering: %02"PRIu32":%02"PRIu32":%02"PRIu32"", in secumod_it_handler()
H A Dstm32_tamp.c799 DMSG("Protection Zone 1-RIF2 begins at register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
801 DMSG("Protection Zone 1-RIF2 ends at register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
805 DMSG("Protection Zone 2-RIF1 begins at register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
807 DMSG("Protection Zone 2-RIF2 begins at register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
809 DMSG("Protection Zone 2-RIF2 ends at register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
814 DMSG("Protection Zone 3-RIF1 begins at register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
816 DMSG("Protection Zone 3-RIF0 begins at register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
818 DMSG("Protection Zone 3-RIF2 begins at register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
820 DMSG("Protection Zone 3-RIF2 ends at the last register: %"PRIu32, in stm32_tamp_apply_bkpr_rif_conf()
1057 FMSG("\n \t Date: %"PRIu32"/%"PRIu32"\n \t Time: %"PRIu32":%"PRIu32":%"PRIu32, in stm32_tamp_it_handler()
[all …]
/optee_os/core/arch/arm/plat-rzn1/
H A Dpsci.c52 DMSG("core_id: %" PRIu32, core_id); in psci_cpu_on()
65 DMSG("core_id: %" PRIu32, get_core_pos()); in psci_cpu_off()
/optee_os/core/arch/arm/plat-rockchip/
H A Dpsci_rk322x.c112 EMSG("PLL can't lock, index = %" PRIu32, pll); in pll_wait_lock()
259 DMSG("core_id: %" PRIu32, core_idx); in psci_cpu_on()
268 EMSG("Can't wait cpu%" PRIu32 " wfei before softrst", in psci_cpu_on()
287 EMSG("Can't wait cpu%" PRIu32 " wfei after softrst", core_idx); in psci_cpu_on()
309 DMSG("core_id: %" PRIu32, core); in psci_cpu_off()
327 DMSG("core_id: %" PRIu32 " STATUS: %" PRIx32 " MASK: %" PRIx32, in psci_affinity_info()
/optee_os/core/pta/stm32mp/
H A Dbsec_pta.c69 FMSG("Read shadow %"PRIu32" val: %#"PRIx32, otp_id, in bsec_read_mem()
78 FMSG("Read fuse %"PRIu32" val: %#"PRIx32, otp_id, *buf); in bsec_read_mem()
116 FMSG("Read lock %"PRIu32" val: %#"PRIx32, otp_id, *buf); in bsec_read_mem()
119 FMSG("%"PRIu32" invalid operation: %"PRIu32, otp_id, in bsec_read_mem()
/optee_os/core/drivers/pm/imx/
H A Dpsci.c78 IMSG("core_id: %" PRIu32, core_id); in psci_cpu_off()
105 DMSG("cpu: %" PRIu32 "GPR: %" PRIx32, cpu, imx_get_src_gpr_arg(cpu)); in psci_affinity_info()
/optee_os/core/arch/arm/plat-marvell/armada7k8k/
H A Dhal_sec_perf.c226 DMSG("Range Num%" PRIu32 in _dump_range()
232 DMSG("Size: %" PRIu32 "K, %" PRIu32 "M", sizek, sizem); in _dump_range()
233 DMSG("Perm: %" PRIu32, perm_read); in _dump_range()
/optee_os/core/pta/
H A Dgprof.c133 DMSG("TA sampling stats: sample count=%" PRIu32 " user time=%" PRIu64 in gprof_stop_pc_sampling()
134 " cntfrq=%" PRIu32 " rate=%" PRIu32, sbuf->count, sbuf->usr, in gprof_stop_pc_sampling()
/optee_os/core/drivers/firewall/
H A Dstm32_etzpc.c181 IMSG("WARNING: RCC tzen:0, insecure ETZPC hardening %"PRIu32":%s", in sanitize_decprot_config()
189 IMSG("WARNING: RCC tzen:%u mckprot:%u, insecure ETZPC hardening %"PRIu32":%s", in sanitize_decprot_config()
216 FMSG("ID : %"PRIu32", config %i", decprot_id, attr); in etzpc_configure_decprot()
620 EMSG("Invalid TZMA mode %"PRIu32, mode); in stm32_etzpc_configure_memory()
642 EMSG("Unknown firewall ID: %"PRIu32, id); in stm32_etzpc_configure_memory()
679 DMSG("Compliant locked config for periph %"PRIu32" - attr %s", in stm32_etzpc_configure()
690 DMSG("Setting access config for periph %"PRIu32" - attr %s", id, in stm32_etzpc_configure()
699 EMSG("Unknown firewall ID: %"PRIu32, id); in stm32_etzpc_configure()
744 DMSG("Invalid DECPROT %"PRIu32, id); in fdt_etzpc_conf_decprot()
H A Dstm32_rifsc.c326 DMSG("RIFSC version %"PRIu32".%"PRIu32, in stm32_rifsc_get_driverdata()
553 DMSG("Locking RIF conf for peripheral ID: %"PRIu32, in stm32_risup_cfg()
610 EMSG("A CID should be set for RIMU %"PRIu32, rimu->id); in stm32_rimu_errata_ahbrisab()
621 EMSG("RIMU %"PRIu32" cannot be set in inheritance mode", in stm32_rimu_errata_ahbrisab()
649 EMSG("RIMU %"PRIu32" in inheritance mode with CID0", in stm32_rimu_errata_ahbrisab()
941 FMSG("RIF semaphore %s for ID: %"PRIu32, in stm32_rifsc_sem_pm_suspend()
985 EMSG("Could not acquire semaphore for resource %"PRIu32, in stm32_rifsc_sem_pm_resume()
/optee_os/core/arch/arm/plat-marvell/armada3700/
H A Dhal_sec_perf.c216 DMSG("Range Num%" PRIu32 in _dump_range()
220 DMSG("Size: %" PRIu32 "M", (0x1 << sizecode_read)); in _dump_range()
221 DMSG("Perm: %" PRIu32, perm_read); in _dump_range()
/optee_os/core/lib/scmi-server/
H A Dscmi_reset_consumer.c94 EMSG("Domain ID %"PRIu32" already used", domain_id); in optee_scmi_server_init_resets()
99 DMSG("scmi reset shares %s on domain ID %"PRIu32, in optee_scmi_server_init_resets()
/optee_os/core/tests/
H A Dnotif_test_wd.c136 DMSG("seconds %"PRIu32" millis %"PRIu32" count %u", in periodic_callback()
/optee_os/core/drivers/crypto/caam/hal/ls/
H A Dhal_jr.c23 HAL_TRACE("JR%" PRIu32 "MIDR_MS value 0x%" PRIx32, jr_idx, val); in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/
H A Dcaam_rng.c161 RNG_TRACE("Instantiation start at SH%" PRIu32 " (%" PRIu32 ")", sh_idx, in prepare_inst_desc()
280 RNG_TRACE("RNG Kick (inc=%" PRIu32 ") ret 0x%08x", in caam_rng_instantiation()
H A Dcaam_pwr.c125 PWR_TRACE("CAAM power mode %" PRIu32 " entry", pm_hint); in pm_enter()
149 PWR_TRACE("CAAM power mode %" PRIu32 " resume", pm_hint); in pm_resume()
/optee_os/ta/pkcs11/src/
H A Dpkcs11_token.c406 n = snprintf(sn, sizeof(sn), "%0*"PRIu32, in entry_ck_token_info()
435 DMSG("PKCS11 token %"PRIu32": mechanism 0x%04"PRIx32": %s", in dmsg_print_supported_mechanism()
540 DMSG("PKCS11 token %"PRIu32": mechanism 0x%"PRIx32" info", in entry_ck_token_mecha_info()
681 DMSG("Open PKCS11 session %"PRIu32, session->handle); in entry_ck_open_session()
703 DMSG("Close PKCS11 session %"PRIu32, session->handle); in close_ck_session()
768 DMSG("Close all sessions for PKCS11 token %"PRIu32, token_id); in entry_ck_close_all_sessions()
812 DMSG("Get find on PKCS11 session %"PRIu32, session->handle); in entry_ck_session_info()
864 IMSG("Token %"PRIu32": SO PIN locked", token_id); in entry_ck_token_initialize()
967 IMSG("PKCS11 token %"PRIu32": initialized", token_id); in entry_ck_token_initialize()
1126 IMSG("PKCS11 session %"PRIu32": init PIN", session->handle); in entry_ck_init_pin()
[all …]
/optee_os/lib/libutils/isoc/include/
H A Dinttypes.h38 #define PRIu32 "u" macro
/optee_os/core/drivers/amd/
H A Dgpio_common.c33 EMSG("Invalid GPIO pin number: %"PRIu32, gpio); in amd_gpio_get_bank_and_pin()

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