Searched refs:pllcfgr (Results 1 – 3 of 3) sorted by relevance
123 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ in configure_clocks()138 uint32_t pllcfgr = 0; in configure_clocks() local139 pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */ in configure_clocks()140 pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT; in configure_clocks()141 pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; in configure_clocks()142 pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; in configure_clocks()143 pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; in configure_clocks()144 writel(pllcfgr, ®s->pllcfgr); in configure_clocks()191 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); in stm32_clk_get_rate()192 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) in stm32_clk_get_rate()[all …]
149 writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */ in configure_clocks()171 &STM32_RCC->pllcfgr); in configure_clocks()172 setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC); in configure_clocks()205 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); in clock_get()206 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) in clock_get()208 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) in clock_get()
42 u32 pllcfgr; /* RCC PLL configuration */ member