123 	writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */  in configure_clocks()
138 	uint32_t pllcfgr = 0;  in configure_clocks()  local
139 	pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */  in configure_clocks()
140 	pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;  in configure_clocks()
141 	pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;  in configure_clocks()
142 	pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;  in configure_clocks()
143 	pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;  in configure_clocks()
144 	writel(pllcfgr, &regs->pllcfgr);  in configure_clocks()
191 		pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);  in stm32_clk_get_rate()
192 		plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)  in stm32_clk_get_rate()
194 		pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)  in stm32_clk_get_rate()