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Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL5 (Results 1 – 2 of 2) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/
H A Dxusb-padctl.c199 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 macro
229 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
232 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in pcie_phy_enable()
/OK3568_Linux_fs/kernel/drivers/phy/tegra/
H A Dxusb-tegra210.c183 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370 macro
287 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
292 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()