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Searched refs:SET_BIT (Results 1 – 23 of 23) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/net/ethernet/sfc/
H A Dmcdi_port_common.c116 #define SET_BIT(name) __set_bit(ETHTOOL_LINK_MODE_ ## name ## _BIT, \ in mcdi_to_ethtool_linkset() macro
122 SET_BIT(Backplane); in mcdi_to_ethtool_linkset()
124 SET_BIT(1000baseKX_Full); in mcdi_to_ethtool_linkset()
126 SET_BIT(10000baseKX4_Full); in mcdi_to_ethtool_linkset()
128 SET_BIT(40000baseKR4_Full); in mcdi_to_ethtool_linkset()
134 SET_BIT(FIBRE); in mcdi_to_ethtool_linkset()
136 SET_BIT(1000baseT_Full); in mcdi_to_ethtool_linkset()
137 SET_BIT(1000baseX_Full); in mcdi_to_ethtool_linkset()
140 SET_BIT(10000baseCR_Full); in mcdi_to_ethtool_linkset()
141 SET_BIT(10000baseLR_Full); in mcdi_to_ethtool_linkset()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/kyro/
H A DSTG4000VTG.c34 tmp |= SET_BIT(8); in DisableVGA()
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); in StopVTG()
53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); in StartVTG()
157 tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1); in SetupVTG()
H A DSTG4000Ramdac.c104 tmp &= ~SET_BIT(31); in InitialiseRamdac()
152 tmp = (STG_READ_REG(DACStreamCtrl)) & ~SET_BIT(0); in DisableRamdacOutput()
161 tmp = (STG_READ_REG(DACStreamCtrl)) | SET_BIT(0); in EnableRamdacOutput()
H A DSTG4000InitDevice.c296 tmp |= SET_BIT(14); in SetCoreClockPLL()
306 tmp |= SET_BIT(14); in SetCoreClockPLL()
314 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); in SetCoreClockPLL()
318 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); in SetCoreClockPLL()
H A DSTG4000OverlayDevice.c181 tmp |= SET_BIT(31); /* Overlay format to Planer */ in CreateOverlaySurface()
293 tmp |= SET_BIT(7); in EnableOverlayPlane()
298 tmp |= SET_BIT(1); /* video stream */ in EnableOverlayPlane()
H A DSTG4000Reg.h31 #define SET_BIT(n) (1<<(n)) macro
/OK3568_Linux_fs/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S15 #define SET_BIT(val, bit) ((val) | (1 << (bit))) macro
16 #define SET_PLL_PD(val) SET_BIT(val, 30)
17 #define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16)
18 #define PLL_BYPASS(val) SET_BIT(val, 2)
/OK3568_Linux_fs/external/xserver/glx/
H A Dextension_string.c37 #define SET_BIT(m,b) (m[ (b) / 8 ] |= (1U << ((b) % 8))) macro
162 SET_BIT(enable_bits, known_glx_extensions[i].bit); in __glXEnableExtension()
177 SET_BIT(enable_bits, known_glx_extensions[i].bit); in __glXInitExtensionEnableBits()
/OK3568_Linux_fs/kernel/drivers/usb/storage/
H A Drealtek_cr.c120 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
574 SET_BIT(value, 2); in config_autodelink_after_power_on()
579 SET_BIT(value, 7); in config_autodelink_after_power_on()
592 SET_BIT(value, 2); in config_autodelink_after_power_on()
639 SET_BIT(value, 2); in config_autodelink_before_power_down()
655 SET_BIT(value, 0); in config_autodelink_before_power_down()
657 SET_BIT(value, 2); in config_autodelink_before_power_down()
671 SET_BIT(value, 0); in config_autodelink_before_power_down()
672 SET_BIT(value, 7); in config_autodelink_before_power_down()
676 SET_BIT(value, 2); in config_autodelink_before_power_down()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_ring2.c19 ring_cfg[3] |= SET_BIT(X2_DEQINTEN); in xgene_enet_ring_init()
31 ring_cfg[5] |= SET_BIT(X2_QBASE_AM) | SET_BIT(X2_MSG_AM); in xgene_enet_ring_init()
H A Dxgene_enet_main.c106 SET_BIT(COHERENT)); in xgene_enet_refill_pagepool()
157 SET_BIT(COHERENT)); in xgene_enet_refill_bufpool()
360 *hopinfo |= SET_BIT(ET) | SET_VAL(MSS, mss_index); in xgene_enet_work_msg()
373 SET_BIT(IC) | in xgene_enet_work_msg()
374 SET_BIT(TYPE_ETH_WORK_MESSAGE); in xgene_enet_work_msg()
447 SET_BIT(COHERENT)); in xgene_enet_setup_tx_desc()
/OK3568_Linux_fs/kernel/drivers/scsi/sym53c8xx_2/
H A Dsym_nvram.c235 #define SET_BIT 0 macro
248 case SET_BIT: in S24C16_set_bit()
272 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_start()
284 S24C16_set_bit(np, 1, gpreg, SET_BIT); in S24C16_stop()
294 S24C16_set_bit(np, write_bit, gpreg, SET_BIT); in S24C16_do_bit()
488 #undef SET_BIT
/OK3568_Linux_fs/kernel/include/linux/mdio/
H A Dmdio-xgene.h107 #define SET_BIT(field) \ macro
/OK3568_Linux_fs/kernel/drivers/crypto/qat/qat_common/
H A Dqat_hal.c154 #define SET_BIT(wrd, bit) (wrd | 1 << bit) macro
170 SET_BIT(csr, CE_INUSE_CONTEXTS_BITPOS) : in qat_hal_set_ae_ctx_mode()
185 SET_BIT(csr, CE_NN_MODE_BITPOS) : in qat_hal_set_ae_nn_mode()
205 SET_BIT(csr, CE_LMADDR_0_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
210 SET_BIT(csr, CE_LMADDR_1_GLOBAL_BITPOS) : in qat_hal_set_ae_lm_mode()
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.h16 #define SET_BIT(data, bit) ((data) | (0x1 << (bit))) macro
H A Dhigh_speed_env_spec.c1405 data = SET_BIT(data, 9); in hws_pre_serdes_init_config()
1463 data = SET_BIT(data, bit_off); in serdes_polarity_config()
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/ssv6xxx/smac/
H A Dap.c33 #define SET_BIT(v,b) ( (v) |= (0x01<<b) ) macro
213 SET_BIT(sc->beacon_usage, avl_bcn_type); in ssv6xxx_beacon_set()
/OK3568_Linux_fs/kernel/drivers/input/touchscreen/gt1x/
H A Dgt1x_generic.c1191 SET_BIT(cur_event, BIT_STYLUS_KEY); in gt1x_touch_event_handler()
1193 SET_BIT(cur_event, BIT_TOUCH_KEY); in gt1x_touch_event_handler()
1199 SET_BIT(cur_event, BIT_STYLUS); in gt1x_touch_event_handler()
1203 SET_BIT(cur_event, BIT_TOUCH); in gt1x_touch_event_handler()
H A Dgt1x_generic.h439 #define SET_BIT(data, flag) ((data) |= (flag)) macro
/OK3568_Linux_fs/kernel/drivers/staging/rts5208/
H A Drtsx_chip.h325 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) macro
H A Drtsx_scsi.c421 SET_BIT(chip->lun_mc, lun); in test_unit_ready()
857 SET_BIT(chip->lun_mc, lun); in read_write()
1058 SET_BIT(chip->lun_mc, lun); in read_capacity()
H A Dsd.c3770 SET_BIT(chip->lun_mc, lun);
/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-qup.c120 #define SET_BIT 0x1 macro