Searched refs:SC_MPLLCTRL (Results 1 – 2 of 2) sorted by relevance
17 #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* DSP */ macro29 uniphier_ld20_sscpll_init(SC_MPLLCTRL, 1600, 1, 2); /* 1500MHz -> 1600MHz */ in uniphier_ld11_pll_init()32 uniphier_ld20_sscpll_set_regi(SC_MPLLCTRL, 5); in uniphier_ld11_pll_init()37 uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL); in uniphier_ld11_pll_init()
18 #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */ macro38 uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); in uniphier_ld20_pll_init()46 uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL); in uniphier_ld20_pll_init()