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Searched refs:RK3562_VP0_MCU_CTRL (Results 1 – 3 of 3) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip_vop2.c435 #define RK3562_VP0_MCU_CTRL 0xCF8 macro
3528 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
3530 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_mode_setup()
3532 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK, in vop3_mcu_mode_setup()
3534 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK, in vop3_mcu_mode_setup()
3536 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK, in vop3_mcu_mode_setup()
3538 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK, in vop3_mcu_mode_setup()
3540 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK, in vop3_mcu_mode_setup()
3550 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
3552 vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK, in vop3_mcu_bypass_mode_setup()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c1022 .mcu_pix_total = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 0),
1023 .mcu_cs_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 6),
1024 .mcu_cs_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 10),
1025 .mcu_rw_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 16),
1026 .mcu_rw_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 20),
1027 .mcu_hold_mode = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 27),
1028 .mcu_frame_st = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 28),
1029 .mcu_rs = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 29),
1030 .mcu_bypass = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 30),
1031 .mcu_type = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 31),
H A Drockchip_vop_reg.h1138 #define RK3562_VP0_MCU_CTRL 0xCF8 macro