Searched refs:REG_SET_5x01_0_8_CML_MODE (Results 1 – 2 of 2) sorted by relevance
147 #define REG_SET_5x01_0_8_CML_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x01 , val , 0 , 8 ) macro
551 REG_SET_5x01_0_8_CML_MODE( ch, param->cml_mode ); in vd_vi_clock_set_seq9()