1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /******************************************************************************** 3 * 4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved. 5 * Module : Jaguar1 Device Driver 6 * Description : coax_table.h 7 * Author : 8 * Date : 9 * Version : Version 1.0 10 * 11 ******************************************************************************** 12 * History : 13 * 14 * 15 ********************************************************************************/ 16 #ifndef _JAGUAR1_REGISTER_SET_DEFINE_ 17 #define _JAGUAR1_REGISTER_SET_DEFINE_ 18 19 #include "jaguar1_video.h" 20 21 22 /*================================================================================================= 23 * 24 * REG_SET_BANKxADDR_StartBit_Size_RegName( Channel, Setting Value ) 25 * 26 *=================================================================================================*/ 27 28 29 // vd_jaguar1_init_set 30 #define REG_SET_0x00_0_8_EACH_SET(ch, val) vd_register_set ( 0 , 0x00 , 0x00 + ch , val , 0 , 8 ) 31 32 // vd_jaguar1_single_differ_set 33 #define REG_SET_0x18_0_8_EX_CBAR_ON(ch, val) vd_register_set ( 0 , 0x00 , 0x18 + ch , val , 0 , 8 ) 34 #define REG_SET_5x00_0_8_CMP(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x00 , val , 0 , 8 ) 35 #define REG_SET_5x01_0_8_CML(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x01 , val , 0 , 8 ) 36 #define REG_SET_5x1D_0_8_AFE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x1d , val , 0 , 8 ) 37 #define REG_SET_5x92_0_8_PWM(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x92 , val , 0 , 8 ) 38 39 // vd_vo_port_y_c_merge_set 40 #define REG_SET_1xEC_0_8_yc_merge(ch, val) vd_register_set ( 0 , 0x01 , 0xec + ch , val , 0 , 8 ) 41 42 // vd_vo_mux_mode_set 43 #define REG_SET_1xC8_0_8_out_sel(ch, val) vd_register_set ( 0 , 0x01 , 0xc8 + ch , val , 0 , 8 ) 44 45 // vd_vo_manual_mode_set 46 47 48 // vd_vi_manual_set_seq1 49 #define REG_SET_1x7C_0_1_clk_auto_1(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 0 , 1 ) 50 #define REG_SET_1x7C_1_1_clk_auto_2(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 1 , 1 ) 51 #define REG_SET_1x7C_2_1_clk_auto_3(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 2 , 1 ) 52 #define REG_SET_1x7C_3_1_clk_auto_4(ch, val) vd_register_set ( 0 , 0x01 , 0x7c , val , 3 , 1 ) 53 54 #define REG_SET_5x32_0_8_NOVIDEO_DET_A(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x32 , val , 0 , 8 ) 55 #define REG_SET_5xB9_0_8_HAFC_LPF_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xb9 , val , 0 , 8 ) 56 #define REG_SET_9x44_0_8_FSC_EXT_EN(ch, val) vd_register_set ( 0 , 0x09 , 0x44 + ch , val , 0 , 8 ) 57 #define REG_SET_5x6E_0_8_VBLK_END_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x6e , val , 0 , 8 ) 58 #define REG_SET_5x6F_0_8_VBLK_END_EXT(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x6f , val , 0 , 8 ) 59 60 // afe_reg 61 #define REG_SET_5x00_0_8_A_CMP_PW_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x00 , val , 0 , 8 ) 62 #define REG_SET_5x02_0_8_A_CMP_TIMEUNIT(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x02 , val , 0 , 8 ) 63 #define REG_SET_5x1E_0_8_VAFEMD(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x1e , val , 0 , 8 ) 64 #define REG_SET_5x58_0_8_VAFE1_EQ_BAND_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x58 , val , 0 , 8 ) 65 #define REG_SET_5x59_0_8_LPF_BYPASS(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x59 , val , 0 , 8 ) 66 #define REG_SET_5x5A_0_8_VAFE_IMP_CNT(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5a , val , 0 , 8 ) 67 #define REG_SET_5x5B_0_8_VAFE_DUTY(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5b , val , 0 , 8 ) 68 #define REG_SET_5x5C_0_8_VAFE_B_LPF_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5c , val , 0 , 8 ) 69 #define REG_SET_5x94_0_8_PWM_DELAY_H(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x94 , val , 0 , 8 ) 70 #define REG_SET_5x95_0_8_PWM_DELAY_L(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x95 , val , 0 , 8 ) 71 #define REG_SET_5x65_0_8_VAFE_CML_SPEED(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x65 , val , 0 , 8 ) 72 73 74 // vd_vi_format_set_seq3 75 #define REG_SET_0x10_0_8_VD_FMT(ch, val) vd_register_set ( 0 , 0x00 , 0x10 + ch , val , 0 , 8 ) 76 #define REG_SET_0x0C_0_8_SPL_MODE(ch, val) vd_register_set ( 0 , 0x00 , 0x0c + ch , val , 0 , 8 ) 77 #define REG_SET_0x04_0_8_SD_MODE(ch, val) vd_register_set ( 0 , 0x00 , 0x04 + ch , val , 0 , 8 ) 78 #define REG_SET_0x08_0_8_AHD_MODE(ch, val) vd_register_set ( 0 , 0x00 , 0x08 + ch , val , 0 , 8 ) 79 #define REG_SET_5x69_0_1_SD_FREQ_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x69 , val , 0 , 1 ) 80 #define REG_SET_5x62_0_8_SYNC_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x62 , val , 0 , 8 ) 81 82 83 // vd_vi_chroma_set_seq4 84 #define REG_SET_0x5C_0_8_PAL_CM_OFF(ch, val) vd_register_set ( 0 , 0x00 , 0x5c + ch , val , 0 , 8 ) 85 #define REG_SET_5x28_0_8_S_POINT(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x28 , val , 0 , 8 ) 86 #define REG_SET_5x25_0_8_FSC_LOCK_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x25 , val , 0 , 8 ) 87 #define REG_SET_5x90_0_8_COMB_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x90 , val , 0 , 8 ) 88 89 90 // vd_vi_h_timing_set_seq5 91 #define REG_SET_0x68_0_8_H_DLY_LSB(ch, val) vd_register_set ( 0 , 0x00 , 0x68 + ch , val , 0 , 8 ) 92 #define REG_SET_0x6c_0_8_H_DLY_MSB(ch, val) vd_register_set ( 0 , 0x00 , 0x6c + ch , val , 0 , 8 ) 93 #define REG_SET_0x60_0_8_Y_DLY(ch, val) vd_register_set ( 0 , 0x00 , 0x60 + ch , val , 0 , 8 ) 94 #define REG_SET_0x78_0_8_V_BLK_END_A(ch, val) vd_register_set ( 0 , 0x00 , 0x78 + ch , val , 0 , 8 ) 95 #define REG_SET_5x38_4_1_H_MASK_ON(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x38 , val , 4 , 1 ) 96 #define REG_SET_5x38_0_4_H_MASK_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x38 , val , 0 , 4 ) 97 #define REG_SET_0x64_0_8_V_BLK_END_B(ch, val) vd_register_set ( 0 , 0x00 , 0x64 + ch , val , 0 , 8 ) 98 #define REG_SET_0x14_4_1_FLD_INV(ch, val) vd_register_set ( 0 , 0x00 , 0x14 + ch , val , 4 , 1 ) 99 #define REG_SET_5x64_0_8_MEM_RDP(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x64 , val , 0 , 8 ) 100 #define REG_SET_5x47_0_8_SYNC_RS(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x47 , val , 0 , 8 ) 101 #define REG_SET_5xA9_0_8_V_BLK_END_B(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xa9 , val , 0 , 8 ) 102 103 104 // vd_vi_h_scaler_mode_set_seq6 105 #define REG_SET_5x53_2_2_LINEMEM_MD(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x53 , val , 2 , 2 ) 106 #define REG_SET_9x96_0_8_H_DOWN_SCALER(ch, val) vd_register_set ( 0 , 0x09 , 0x96 + (0x20 * ch) , val , 0 , 8 ) 107 #define REG_SET_9x97_0_8_H_SCALER_MODE(ch, val) vd_register_set ( 0 , 0x09 , 0x97 + (0x20 * ch) , val , 0 , 8 ) 108 #define REG_SET_9x98_0_8_REF_BASE_LSB(ch, val) vd_register_set ( 0 , 0x09 , 0x98 + (0x20 * ch) , val , 0 , 8 ) 109 #define REG_SET_9x99_0_8_REF_BASE_MSB(ch, val) vd_register_set ( 0 , 0x09 , 0x99 + (0x20 * ch) , val , 0 , 8 ) 110 #define REG_SET_9x9E_0_8_H_SCALER_OUTPUT_H_ACTIVE(ch, val) vd_register_set ( 0 , 0x09 , 0x9e + (0x20 * ch) , val , 0 , 8 ) 111 112 113 //vd_vi_hpll_set_seq7 114 #define REG_SET_5x50_0_8_HPLL_MASK_ON(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x50 , val , 0 , 8 ) 115 #define REG_SET_5xB8_0_8_HAFC_OP_MD(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xb8 , val , 0 , 8 ) 116 #define REG_SET_5xBB_0_8_HAFC_BYP_TH_E(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xbb , val , 0 , 8 ) 117 #define REG_SET_5xB7_0_8_HAFC_BYP_TH_S(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xb7 , val , 0 , 8 ) 118 119 // vd_vi_color_set_seq8 120 #define REG_SET_0x20_0_8_BRIGHTNESS(ch, val) vd_register_set ( 0 , 0x00 , 0x20 + ch , val , 0 , 8 ) 121 #define REG_SET_0x24_0_8_CONTARST(ch, val) vd_register_set ( 0 , 0x00 , 0x24 + ch , val , 0 , 8 ) 122 #define REG_SET_0x28_0_8_BLACK_LEVEL(ch, val) vd_register_set ( 0 , 0x00 , 0x28 + ch , val , 0 , 8 ) 123 #define REG_SET_0x58_0_8_SATURATION_A(ch, val) vd_register_set ( 0 , 0x00 , 0x58 + ch , val , 0 , 8 ) 124 #define REG_SET_0x40_0_8_HUE(ch, val) vd_register_set ( 0 , 0x00 , 0x40 + ch , val , 0 , 8 ) 125 #define REG_SET_0x44_0_8_U_GAIN(ch, val) vd_register_set ( 0 , 0x00 , 0x44 + ch , val , 0 , 8 ) 126 #define REG_SET_0x48_0_8_V_GAIN(ch, val) vd_register_set ( 0 , 0x00 , 0x48 + ch , val , 0 , 8 ) 127 #define REG_SET_0x4C_0_8_U_OFFSET(ch, val) vd_register_set ( 0 , 0x00 , 0x4c + ch , val , 0 , 8 ) 128 #define REG_SET_0x50_0_8_V_OFFSET(ch, val) vd_register_set ( 0 , 0x00 , 0x50 + ch , val , 0 , 8 ) 129 #define REG_SET_5x2B_0_8_SATURATION_B(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x2b , val , 0 , 8 ) 130 #define REG_SET_5x24_0_8_BURSET_DEC_A(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x24 , val , 0 , 8 ) 131 #define REG_SET_5x5F_0_8_BURSET_DEC_B(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5f , val , 0 , 8 ) 132 #define REG_SET_5xD1_0_8_BURSET_DEC_C(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xd1 , val , 0 , 8 ) 133 #define REG_SET_9x44_0_8_FSC_EXT_EN(ch, val) vd_register_set ( 0 , 0x09 , 0x44 + ch , val , 0 , 8 ) 134 #define REG_SET_9x50_0_8_FSC_EXT_VAL_7_0(ch, val) vd_register_set ( 0 , 0x09 , 0x50 + (ch*4) , val , 0 , 8 ) 135 #define REG_SET_9x51_0_8_FSC_EXT_VAL_15_8(ch, val) vd_register_set ( 0 , 0x09 , 0x51 + (ch*4) , val , 0 , 8 ) 136 #define REG_SET_9x52_0_8_FSC_EXT_VAL_23_16(ch, val) vd_register_set ( 0 , 0x09 , 0x52 + (ch*4) , val , 0 , 8 ) 137 #define REG_SET_9x53_0_8_FSC_EXT_VAL_31_24(ch, val) vd_register_set ( 0 , 0x09 , 0x53 + (ch*4) , val , 0 , 8 ) 138 #define REG_SET_5x26_0_8_FSC_LOCK_SENSE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x26 , val , 0 , 8 ) 139 #define REG_SET_5xB8_0_8_HPLL_MASK_END(ch, val) vd_register_set ( 0 , 0x05 + ch , 0xb8 , val , 0 , 8 ) 140 #define REG_SET_9x40_0_8_FSC_DET_MODE(ch, val) vd_register_set ( 0 , 0x09 , 0x40 + ch , val , 0 , 8 ) 141 142 // vd_vi_clock_set_seq9 143 #define REG_SET_1x84_0_8_CLK_ADC(ch, val) vd_register_set ( 0 , 0x01 , 0x84 + ch , val , 0 , 8 ) 144 #define REG_SET_1x88_0_8_CLK_PRE(ch, val) vd_register_set ( 0 , 0x01 , 0x88 + ch , val , 0 , 8 ) 145 #define REG_SET_1x8c_0_8_CLK_POST(ch, val) vd_register_set ( 0 , 0x01 , 0x8c + ch , val , 0 , 8 ) 146 147 #define REG_SET_5x01_0_8_CML_MODE(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x01 , val , 0 , 8 ) 148 #define REG_SET_5x05_0_8_AGC_OP(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x05 , val , 0 , 8 ) 149 #define REG_SET_5x1D_0_8_G_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x1D , val , 0 , 8 ) 150 151 152 // vd_jaguar1_sw_reset 153 #define REG_SET_1x81_0_1_VPLL_RST(ch, val) vd_register_set ( 0 , 0x01 , 0x81 , val , 0 , 1 ) 154 #define REG_SET_1x80_0_1_VPLL_C(ch, val) vd_register_set ( 0 , 0x01 , 0x80 , val , 0 , 1 ) 155 156 157 // __eq_base_set_value 158 #define REG_SET_5x65_0_8_EQ_BYPASS(ch, val) vd_register_set ( 0, 0x05 + ch, 0x65 , val, 0, 8 ) 159 #define REG_SET_5x58_0_8_EQ_BAND_SEL(ch, val) vd_register_set ( 0, 0x05 + ch, 0x58 , val, 0, 8 ) 160 #define REG_SET_5x5C_0_8_EQ_GAIN_SEL(ch, val) vd_register_set ( 0 , 0x05 + ch , 0x5c , val , 0 , 8 ) 161 #define REG_SET_Ax3D_0_8_EQ_DEQ_A_ON(ch, val) vd_register_set ( 0, 0x0a + ((ch%4)/2), 0x3d + (ch%2 * 0x80), val, 0 , 8 ) 162 #define REG_SET_Ax3C_0_8_EQ_DEQ_A_SEL(ch, val) vd_register_set ( 0 , 0x0a + ((ch%4)/2) , 0x3c + (ch%2 * 0x80), val , 0 , 8 ) 163 #define REG_SET_9x80_0_8_EQ_DEQ_B_SEL(ch, val) vd_register_set ( 0 , 0x09 , 0x80 + (ch * 0x20) , val , 0 , 8 ) 164 165 166 // __eq_coeff_set_value 167 #define REG_SET_Ax30_0_8_EQ_DEQ_A_01(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x30 + (ch%2 * 0x80) , val , 0 , 8 ) 168 #define REG_SET_Ax31_0_8_EQ_DEQ_A_02(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x31 + (ch%2 * 0x80) , val , 0 , 8 ) 169 #define REG_SET_Ax32_0_8_EQ_DEQ_A_03(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x32 + (ch%2 * 0x80) , val , 0 , 8 ) 170 #define REG_SET_Ax33_0_8_EQ_DEQ_A_04(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x33 + (ch%2 * 0x80) , val , 0 , 8 ) 171 #define REG_SET_Ax34_0_8_EQ_DEQ_A_05(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x34 + (ch%2 * 0x80) , val , 0 , 8 ) 172 #define REG_SET_Ax35_0_8_EQ_DEQ_A_06(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x35 + (ch%2 * 0x80) , val , 0 , 8 ) 173 #define REG_SET_Ax36_0_8_EQ_DEQ_A_07(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x36 + (ch%2 * 0x80) , val , 0 , 8 ) 174 #define REG_SET_Ax37_0_8_EQ_DEQ_A_08(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x37 + (ch%2 * 0x80) , val , 0 , 8 ) 175 #define REG_SET_Ax38_0_8_EQ_DEQ_A_09(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x38 + (ch%2 * 0x80) , val , 0 , 8 ) 176 #define REG_SET_Ax39_0_8_EQ_DEQ_A_10(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x39 + (ch%2 * 0x80) , val , 0 , 8 ) 177 #define REG_SET_Ax3A_0_8_EQ_DEQ_A_11(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x3a + (ch%2 * 0x80) , val , 0 , 8 ) 178 #define REG_SET_Ax3B_0_8_EQ_DEQ_A_12(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x3b + (ch%2 * 0x80) , val , 0 , 8 ) 179 180 181 // __eq_color_set_value 182 #define REG_SET_0x24_0_8_EQ_COLOR_CONTRAST(ch, val) vd_register_set( 0, 0x00 , 0x24 + ch , val , 0 , 8 ) 183 #define REG_SET_0x30_0_8_EQ_COLOR_H_PEAKING_1(ch, val) vd_register_set( 0, 0x00 , 0x30 + ch , val , 0 , 8 ) 184 #define REG_SET_0x34_0_8_EQ_COLOR_H_PEAKING_2(ch, val) vd_register_set( 0, 0x00 , 0x34 + ch , val , 0 , 8 ) 185 #define REG_SET_0x40_0_8_EQ_COLOR_HUE(ch, val) vd_register_set( 0, 0x00 , 0x40 + ch , val , 0 , 8 ) 186 #define REG_SET_0x44_0_8_EQ_COLOR_U_GAIN(ch, val) vd_register_set( 0, 0x00 , 0x44 + ch , val , 0 , 8 ) 187 #define REG_SET_0x48_0_8_EQ_COLOR_V_GAIN(ch, val) vd_register_set( 0, 0x00 , 0x48 + ch , val , 0 , 8 ) 188 #define REG_SET_0x4C_0_8_EQ_COLOR_U_OFFSET(ch, val) vd_register_set( 0, 0x00 , 0x4c + ch , val , 0 , 8 ) 189 #define REG_SET_0x50_0_8_EQ_COLOR_V_OFFSET(ch, val) vd_register_set( 0, 0x00 , 0x50 + ch , val , 0 , 8 ) 190 #define REG_SET_0x28_0_8_EQ_COLOR_BLACK_LEVEL(ch, val) vd_register_set( 0, 0x00 , 0x28 + ch , val , 0 , 8 ) 191 #define REG_SET_5x31_0_8_EQ_COLOR_C_FILTER(ch, val) vd_register_set( 0, 0x05 + ch , 0x31 , val , 0 , 8 ) 192 #define REG_SET_5x27_0_8_EQ_COLOR_ACC_REF(ch, val) vd_register_set( 0, 0x05 + ch , 0x27 , val , 0 , 8 ) 193 #define REG_SET_5x28_0_8_EQ_COLOR_CTI_DELAY(ch, val) vd_register_set( 0, 0x05 + ch , 0x28 , val , 0 , 8 ) 194 #define REG_SET_5x2b_0_8_EQ_COLOR_SUB_SATURATION(ch, val) vd_register_set( 0, 0x05 + ch , 0x2b , val , 0 , 8 ) 195 #define REG_SET_5x24_0_8_EQ_COLOR_BURST_DEC_A(ch, val) vd_register_set( 0, 0x05 + ch , 0x24 , val , 0 , 8 ) 196 #define REG_SET_5x5F_0_8_EQ_COLOR_BURST_DEC_B(ch, val) vd_register_set( 0, 0x05 + ch , 0x5f , val , 0 , 8 ) 197 #define REG_SET_5xD1_0_8_EQ_COLOR_BURST_DEC_C(ch, val) vd_register_set( 0, 0x05 + ch , 0xd1 , val , 0 , 8 ) 198 #define REG_SET_5xD5_0_8_EQ_COLOR_C_OPTION(ch, val) vd_register_set( 0, 0x05 + ch , 0xd5 , val , 0 , 8 ) 199 #define REG_SET_Ax25_0_8_EQ_COLOR_Y_FILTER_B(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x25 + (ch%2 * 0x80) , val , 0 , 8 ) 200 #define REG_SET_Ax27_0_8_EQ_COLOR_Y_FILTER_B_SEL(ch, val) vd_register_set( 0, 0x0a + ((ch%4)/2) , 0x27 + (ch%2 * 0x80) , val , 0 , 8 ) 201 202 203 // __eq_clk_set_value 204 #define REG_SET_1x84_0_8_EQ_CLOCK_ADC_CLK(ch, val) vd_register_set( 0, 0x01 , 0x84 + ch , val , 0 , 8 ) 205 #define REG_SET_1x88_0_8_EQ_CLOCK_PRE_CLK(ch, val) vd_register_set( 0, 0x01 , 0x88 + ch , val , 0 , 8 ) 206 #define REG_SET_1x8C_0_8_EQ_CLOCK_POST_CLK(ch, val) vd_register_set( 0, 0x01 , 0x8C + ch , val , 0 , 8 ) 207 208 209 // eq_timing_b_set_value 210 #define REG_SET_9x96_0_8_EQ_TIMING_B_HSCALER_1(ch, val) vd_register_set( 0, 0x09 , 0x96 + (ch * 0x20) , val , 0 , 8 ) 211 #define REG_SET_9x97_0_8_EQ_TIMING_B_HSCALER_2(ch, val) vd_register_set( 0, 0x09 , 0x97 + (ch * 0x20) , val , 0 , 8 ) 212 #define REG_SET_9x98_0_8_EQ_TIMING_B_HSCALER_3(ch, val) vd_register_set( 0, 0x09 , 0x98 + (ch * 0x20) , val , 0 , 8 ) 213 #define REG_SET_9x99_0_8_EQ_TIMING_B_HSCALER_4(ch, val) vd_register_set( 0, 0x09 , 0x99 + (ch * 0x20) , val , 0 , 8 ) 214 #define REG_SET_9x9A_0_8_EQ_TIMING_B_HSCALER_5(ch, val) vd_register_set( 0, 0x09 , 0x9a + (ch * 0x20) , val , 0 , 8 ) 215 #define REG_SET_9x9B_0_8_EQ_TIMING_B_HSCALER_6(ch, val) vd_register_set( 0, 0x09 , 0x9b + (ch * 0x20) , val , 0 , 8 ) 216 #define REG_SET_9x9C_0_8_EQ_TIMING_B_HSCALER_7(ch, val) vd_register_set( 0, 0x09 , 0x9c + (ch * 0x20) , val , 0 , 8 ) 217 #define REG_SET_9x9D_0_8_EQ_TIMING_B_HSCALER_8(ch, val) vd_register_set( 0, 0x09 , 0x9d + (ch * 0x20) , val , 0 , 8 ) 218 #define REG_SET_9x9E_0_8_EQ_TIMING_B_HSCALER_9(ch, val) vd_register_set( 0, 0x09 , 0x9e + (ch * 0x20) , val , 0 , 8 ) 219 #define REG_SET_9x40_0_8_EQ_TIMING_B_PN_AUTO(ch, val) vd_register_set( 0, 0x09 , 0x40 + ch , val , 0 , 8 ) 220 #define REG_SET_5x90_0_8_EQ_TIMINING_B_COMB_MODE(ch, val) vd_register_set( 0, 0x05 + ch , 0x90 , val , 0 , 8 ) 221 #define REG_SET_5xB9_0_8_EQ_TIMING_B_HPLL_OP_A(ch, val) vd_register_set( 0, 0x05 + ch , 0xb9 , val , 0 , 8 ) 222 #define REG_SET_5x57_0_8_EQ_TIMING_B_MEM_PATH(ch, val) vd_register_set( 0, 0x05 + ch , 0x57 , val , 0 , 8 ) 223 #define REG_SET_5x25_0_8_EQ_TIMING_B_FSC_LOCK_SPD(ch, val) vd_register_set( 0, 0x05 + ch , 0x25 , val , 0 , 8 ) 224 #define REG_SET_0x04_0_8_EQ_TIMING_B_SD_MD(ch, val) vd_register_set( 0, 0x00 , 0x04 + ch , val , 0 , 8 ) 225 #define REG_SET_0x08_0_8_EQ_TIMING_B_AHD_MD(ch, val) vd_register_set( 0, 0x00 , 0x08 + ch , val , 0 , 8 ) 226 #define REG_SET_0x0C_0_8_EQ_TIMING_B_SPECIAL_MD(ch, val) vd_register_set( 0, 0x00 , 0x0c + ch , val , 0 , 8 ) 227 #define REG_SET_0x78_0_8_EQ_TIMING_B_VBLK_END(ch, val) vd_register_set( 0, 0x00 , 0x78 + ch , val , 0 , 8 ) 228 229 230 #define REG_SET_5x53_2_2_EQ_SD_LINE_MEM_MD(ch, val) vd_register_set( 0, 0x05 + ch , 0x53 , val , 2 , 2 ) 231 #define REG_SET_0x14_4_1_EQ_SD_FLD_INV(ch, val) vd_register_set( 0, 0x00 , 0x14 + ch , val , 4 , 1 ) 232 #define REG_SET_5x2F_7_1_EQ_SD_AUTO(ch, val) vd_register_set( 0, 0x05 + ch , 0x2f , val , 7 , 1 ) 233 #define REG_SET_0x10_0_8_EQ_VIDEO_FORMAT(ch, val) vd_register_set( 0, 0x00 , 0x10 + ch , val , 0 , 8 ) 234 #define REG_SET_5x64_0_8_EQ_MEM_RDP(ch, val) vd_register_set( 0, 0x05 + ch , 0x64 + ch , val , 0 , 8 ) 235 #define REG_SET_5x69_0_1_EQ_SD_FREQ_SEL(ch, val) vd_register_set( 0, 0x05 + ch , 0x69 , val , 0 , 1 ) 236 237 #define REG_SET_0x68_0_8_EQ_TIMING_A_H_DELAY_A(ch, val) vd_register_set( 0, 0x00 , 0x68 + ch , val , 0 , 8 ) 238 #define REG_SET_5x38_0_8_EQ_TIMING_A_H_DELAY_B(ch, val) vd_register_set( 0, 0x05 + ch , 0x38 , val , 0 , 8 ) 239 #define REG_SET_0x6C_0_4_EQ_TIMING_A_H_DELAY_C(ch, val) vd_register_set( 0, 0x00 , 0x6C + ch , val , 0 , 4 ) 240 #define REG_SET_0x64_0_8_EQ_TIMING_A_Y_DELAY(ch, val) vd_register_set( 0, 0x00 , 0x64 + ch , val , 0 , 8 ) 241 242 // ADD 243 #define REG_SET_0x7C_0_8_HZOOM(ch, val) vd_register_set( 0, 0x00 , 0x7c + ch , val , 0 , 8 ) 244 #define REG_SET_5x31_0_8_EQ_C_FILTER(ch, val) vd_register_set( 0, 0x05 + ch , 0x31 , val , 0 , 8 ) 245 #define REG_SET_0x5c_0_8_EQ_PAL_CM_OFF(ch, val) vd_register_set( 0, 0x00 , 0x5c + ch , val , 0 , 8 ) 246 247 #define REG_SET_5x1D_0_8_EQ_AFE_G_SEL(ch, val) vd_register_set( 0, 0x05 + ch , 0x1d , val , 0 , 8 ) 248 #define REG_SET_5x01_0_8_EQ_AFE_CTR_CLP(ch, val) vd_register_set( 0, 0x05 + ch , 0x01 , val , 0 , 8 ) 249 #define REG_SET_5x05_0_8_EQ_D_AGC_OPTION(ch, val) vd_register_set( 0, 0x05 + ch , 0x05 , val , 0 , 8 ) 250 251 #define REG_SET_0x70_0_8_V_DELAY(ch, val) vd_register_set( 0, 0x00 , 0x70 + ch , val , 0 , 8 ) 252 253 #define REG_SET_0x14_0_8_FLD_INV_CHID(ch, val) vd_register_set( 0, 0x00, 0x14 + ch, val + ch, 0, 8) 254 #define REG_SET_0x34_0_8_Y_FIR_MODE(ch, val) vd_register_set( 0, 0x00, 0x34 + ch, val, 0, 8) 255 #define REG_SET_1xA0_0_8_TM_CLK_EN_SET(ch, val) vd_register_set( 0, 0x01, 0xA0 + ch, val, 0, 8 ) 256 #define REG_SET_1xCC_0_8_VPORT_OCLK_SEL_VPORT_OVCLK_DLY_SEL(ch, val) vd_register_set( 0, 0x01, 0xCC + ch, val, 0, 8 ) 257 #define REG_SET_5x21_0_8_CONT_SUB(ch, val) vd_register_set( 0, 0x05 + ch, 0x21, val, 0, 8 ) 258 #define REG_SET_5x55_0_8_C_MEM_CLK_SEL(ch, val) vd_register_set( 0, 0x05 + ch, 0x55, val, 0, 8 ) 259 #define REG_SET_5x56_0_8_FREQ_MEM_CLK_SEL(ch, val) vd_register_set( 0, 0x05 + ch, 0x56, val, 0, 8 ) 260 #define REG_SET_5x57_0_8_LINE_MEM_CLK_INV(ch, val) vd_register_set( 0, 0x05 + ch, 0x57, val, 0, 8 ) 261 #define REG_SET_5xB5_0_8_HAFC_MASK_SEL(ch, val) vd_register_set( 0, 0x05 + ch, 0xB5, val, 0, 8) 262 #define REG_SET_5xB8_0_8_HAFC_HCOEFF_SEL(ch, val) vd_register_set( 0, 0x05 + ch, 0xB8, val, 0, 8) 263 264 /******************************************************************** 265 * End of file 266 ********************************************************************/ 267 268 #endif 269