1 // SPDX-License-Identifier: GPL-2.0
2 /********************************************************************************
3 *
4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved.
5 * Module : video_input.c
6 * Description :
7 * Author :
8 * Date :
9 * Version : Version 1.0
10 *
11 ********************************************************************************
12 * History :
13 *
14 *
15 ********************************************************************************/
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include "jaguar1_common.h"
19 #include "jaguar1_video.h"
20 #include "jaguar1_video_eq.h"
21 #include "jaguar1_video_table.h"
22 #include "jaguar1_coax_protocol.h"
23 #include "jaguar1_reg_set_def.h"
24
25
26 static unsigned char cur_bank = 0xff;
27 static int print_flag = 0;
28
29 /**************************************************************************************
30 * Jaguar1 Video Input initialize value get from table
31 ***************************************************************************************/
__NC_VD_VI_Init_Val_Get(NC_VIVO_CH_FORMATDEF def)32 static NC_VD_VI_Init_STR *__NC_VD_VI_Init_Val_Get( NC_VIVO_CH_FORMATDEF def )
33 {
34 NC_VD_VI_Init_STR *pRet = &vd_vi_init_list[def];
35 if( pRet == NULL )
36 {
37 printk("[DRV]vd_vi_init_list Not Supported format Yet!!!(%d)\n",def);
38 }
39 return pRet;
40 }
41
__NC_VD_VO_Init_Val_Get(NC_VIVO_CH_FORMATDEF def)42 static NC_VD_VO_Init_STR *__NC_VD_VO_Init_Val_Get( NC_VIVO_CH_FORMATDEF def )
43 {
44 NC_VD_VO_Init_STR *pRet = &vd_vo_init_list[def];
45 if( pRet == NULL )
46 {
47 printk("[DRV]vd_vo_init_list Not Supported format Yet!!!(%d)\n",def);
48 }
49 return pRet;
50 }
51
52 /**************************************************************************************
53 * Jaguar1 Register Setting Function
54 *
55 *
56 ***************************************************************************************/
reg_val_print_flag_set(int set)57 void reg_val_print_flag_set( int set )
58 {
59 print_flag = set;
60 }
61
reg_val_print_flag_get(void)62 static int reg_val_print_flag_get( void )
63 {
64 return print_flag;
65 }
66
current_bank_set(unsigned char bank)67 void current_bank_set( unsigned char bank )
68 {
69 cur_bank = bank;
70 }
71
current_bank_get(void)72 unsigned char current_bank_get( void )
73 {
74 return cur_bank;
75 }
76
vd_register_set(int dev,unsigned char bank,unsigned char addr,unsigned char val,int pos,int size)77 void vd_register_set( int dev, unsigned char bank, unsigned char addr, unsigned char val, int pos, int size )
78 {
79 unsigned char ReadVal = 0x00;
80 unsigned char Mask = 0x00;
81 unsigned char rstbit = 0x01;
82 unsigned char WriteVal = val;
83 unsigned char cur_bank = 0x00;
84 int ii =0;
85
86 if( 8 < (pos + size) )
87 {
88 printk("vd_register_set Error!!dev[%d] Bank[0x%02X] Addr[0x%02X] pos[%d] size[%d]\n", dev, bank, addr, pos, size);
89 }
90
91 // Current Bank Get
92 cur_bank = current_bank_get();
93 if( cur_bank != bank )
94 {
95 JAGUAR1_BANK_CHANGE(bank);
96 current_bank_set(bank);
97 }
98
99 // If Data Size 8 Bit, Register Read Skip
100 if( !(pos == 0 && size == 8) )
101 {
102 for(ii=0; ii<size; ii++)
103 {
104 Mask = Mask|(rstbit<<(pos+ii));
105 }
106 Mask = ~Mask;
107 WriteVal = WriteVal<<pos;
108
109 ReadVal = gpio_i2c_read(jaguar1_i2c_addr[dev], addr);
110 ReadVal = ReadVal & Mask;
111 WriteVal = WriteVal | ReadVal;
112 }
113
114 gpio_i2c_write(jaguar1_i2c_addr[dev], addr, WriteVal);
115
116 if( reg_val_print_flag_get() )
117 printk("[DRV]%Xx%02X > 0x%02X\n", current_bank_get(), addr, WriteVal);
118
119 }
120
121 /**************************************************************************************
122 * Jaguar1 Video Input Setting Function
123 *
124 *
125 ***************************************************************************************/
vd_vi_manual_set_seq1(unsigned char dev,unsigned char ch,void * p_param)126 static void vd_vi_manual_set_seq1( unsigned char dev, unsigned char ch, void *p_param )
127 {
128 /*====================================================================
129 * Bank 1x7c
130 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
131 *| | | | | CLK_AUTO_4 | CLK_AUTO_3 | CLK_AUTO_2 | CLK_AUTO_1 |
132 *====================================================================*/
133 /*====================================================================
134 * Bank 0x14
135 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
136 *| | | | FLD_INV_x | CHID_VIN_x |
137 *====================================================================*/
138 /*====================================================================
139 * Bank 0x14
140 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
141 *| | | | FLD_INV_x | CHID_VIN_x |
142 *====================================================================*/
143 /*====================================================================
144 * Bank 5x32
145 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
146 *| | | FLD_DET_MODE | | | NOVID_DET_A |
147 *====================================================================*/
148 /*====================================================================
149 * Bank 13x30 ~ 33 - SK_ing
150 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
151 *| | |det_en |det_en |det_en |det_en |det_en |det_en |
152 *====================================================================*/
153 /*====================================================================
154 * Bank 9x44
155 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
156 *| | | | | | | |FSC_EXT_EN_1 |
157 *====================================================================*/
158 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
159 unsigned char val_13x30;
160 unsigned char val_13x31;
161 unsigned char val_13x32;
162
163 if(ch == 0)
164 REG_SET_1x7C_0_1_clk_auto_1( ch, 0x0 );
165 else if(ch ==1)
166 REG_SET_1x7C_1_1_clk_auto_2( ch, 0x0 );
167 else if(ch ==2)
168 REG_SET_1x7C_2_1_clk_auto_3( ch, 0x0 );
169 else if(ch ==3)
170 REG_SET_1x7C_3_1_clk_auto_4( ch, 0x0 );
171 else
172 printk("[DRV]Clock Auto Set Fail!!:: %x\n", ch);
173
174 REG_SET_5x32_0_8_NOVIDEO_DET_A( ch, 0x10 );
175 REG_SET_5xB9_0_8_HAFC_LPF_SEL( ch, 0xb2 );
176
177 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x13);
178 val_13x30 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x30);
179 val_13x31 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x31);
180 val_13x32 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x32);
181
182 val_13x30 &= (~(1 << (ch + 4)) & (~(1 << ch)));
183 val_13x31 &= (~(1 << (ch + 4)) & (~(1 << ch)));
184 val_13x32 &= (~(1 << ch));
185
186 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x30, val_13x30);
187 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x31, val_13x31);
188 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x32, val_13x32);
189
190 REG_SET_9x44_0_8_FSC_EXT_EN( ch, 0x00 );
191 REG_SET_5x6E_0_8_VBLK_END_SEL( ch, param->vblk_end_sel );
192 REG_SET_5x6F_0_8_VBLK_END_EXT( ch, param->vblk_end_ext );
193
194 }
195
vd_vi_vafe_set_seq2(unsigned char dev,unsigned char ch)196 static void vd_vi_vafe_set_seq2( unsigned char dev, unsigned char ch )
197 {
198 REG_SET_5x00_0_8_A_CMP_PW_MODE( ch, 0xd0 );
199 REG_SET_5x02_0_8_A_CMP_TIMEUNIT( ch, 0x0c );
200 REG_SET_5x1E_0_8_VAFEMD( ch, 0x00 );
201 REG_SET_5x58_0_8_VAFE1_EQ_BAND_SEL( ch, 0x00 );
202 REG_SET_5x59_0_8_LPF_BYPASS( ch, 0x00 );
203 REG_SET_5x5A_0_8_VAFE_IMP_CNT( ch, 0x00 );
204 REG_SET_5x5B_0_8_VAFE_DUTY( ch, 0x41 );
205 REG_SET_5x5C_0_8_VAFE_B_LPF_SEL( ch, 0x78 );
206 REG_SET_5x94_0_8_PWM_DELAY_H( ch, 0x00 );
207 REG_SET_5x95_0_8_PWM_DELAY_L( ch, 0x00 );
208 REG_SET_5x65_0_8_VAFE_CML_SPEED( ch, 0x80 );
209
210 }
211
vd_vi_format_set_seq3(unsigned char dev,unsigned char ch,void * p_param)212 static void vd_vi_format_set_seq3( unsigned char dev, unsigned char ch, void *p_param )
213 {
214 /*============================================================================================
215 * Bank 0x10
216 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
217 *| | BSF_MODE_1 | VIDEO_FORMAT_1 |
218 *============================================================================================*/
219 /*============================================================================================
220 * Bank 0x0c
221 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
222 *| | | | | SPECIAL_MODE |
223 *============================================================================================*/
224 /*============================================================================================
225 * Bank 0x04
226 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
227 *| | | | | SD_MD |
228 *============================================================================================*/
229 /*============================================================================================
230 * Bank 0x08
231 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
232 *| | | | | AHD_MD |
233 *============================================================================================*/
234 /*============================================================================================
235 * Bank 5x69
236 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
237 *| NO_VIDEO_OFF | | OUTPUT PATTERN_ON | MEM_EN | | | | SD_FREQ_SEL |
238 *============================================================================================*/
239 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
240
241 if(ch>3)
242 {
243 printk("[DRV] %s CHID Error\n", __func__);
244 return;
245 }
246
247 REG_SET_0x10_0_8_VD_FMT( ch, param->video_format );
248 REG_SET_0x0C_0_8_SPL_MODE( ch, param->spl_mode );
249 REG_SET_0x04_0_8_SD_MODE( ch, param->sd_mode );
250 REG_SET_0x08_0_8_AHD_MODE( ch, param->ahd_mode );
251 REG_SET_5x69_0_1_SD_FREQ_SEL( ch, param->sd_freq_sel );
252 REG_SET_5x62_0_8_SYNC_SEL( ch, param->sync_sel );
253
254 }
255
vd_vi_chroma_set_seq4(unsigned char dev,unsigned char ch,void * p_param)256 static void vd_vi_chroma_set_seq4( unsigned char dev, unsigned char ch, void *p_param )
257 {
258 /*============================================================================================
259 * Bank 0x5c
260 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
261 *| PAL_CM_OFF | | | COLOROFF | C_KILL |
262 *============================================================================================*/
263 /*============================================================================================
264 * Bank 5x28
265 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
266 *| CTI_CORE_MODE | S_POINT | CTI_DELAY_SEL | | | | |
267 *============================================================================================*/
268 /*============================================================================================
269 * Bank 5x25
270 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
271 *| FSC_LOCK_MODE | FSC_LOCK_SPD |
272 *============================================================================================*/
273 /*============================================================================================
274 * Bank 5x90
275 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
276 *| C_LH_SEL_1 | | YL_SEL_1 | COMB_MODE_1 |
277 *============================================================================================*/
278 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
279
280 if(ch>3)
281 {
282 printk("[DRV] %s CHID Error\n", __func__);
283 return;
284 }
285
286 REG_SET_0x5C_0_8_PAL_CM_OFF( ch, param->pal_cm_off );
287 REG_SET_5x28_0_8_S_POINT( ch, param->s_point );
288 REG_SET_5x25_0_8_FSC_LOCK_MODE( ch, param->fsc_lock_mode );
289 REG_SET_5x90_0_8_COMB_MODE( ch, param->comb_mode );
290
291 }
292
vd_vi_h_timing_set_seq5(unsigned char dev,unsigned char ch,void * p_param)293 static void vd_vi_h_timing_set_seq5( unsigned char dev, unsigned char ch, void *p_param )
294 {
295 /*============================================================================================
296 * Bank 0x68
297 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
298 *| H_DELAY |
299 *============================================================================================*/
300 /*============================================================================================
301 * Bank 0x60
302 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
303 *| | Y_DELAY |
304 *============================================================================================*/
305 /*============================================================================================
306 * Bank 0x78
307 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
308 *| VBLK_END |
309 *============================================================================================*/
310 /*============================================================================================
311 * Bank 5x38
312 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
313 *| | MASK_ON | MASK_SEL1 (Bank0 0x8E[3:0) |
314 *============================================================================================*/
315 /*============================================================================================
316 * Bank 0x64
317 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
318 *| DF_CDELAY | DF_YDELAY |
319 *============================================================================================*/
320 /*============================================================================================
321 * Bank 0x14
322 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
323 *| | FLD_INV | CHID_VIN |
324 *============================================================================================*/
325 /*============================================================================================
326 * Bank 5x64
327 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
328 *| | | | | MEM_RDP_01 |
329 *============================================================================================*/
330 /*============================================================================================
331 * Bank 5x47
332 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
333 *| CONTROL_MODES |
334 *============================================================================================*/
335 /*============================================================================================
336 * Bank 5xa9
337 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
338 *| SIGNED_ADV_STP_DELAY1 | ADV_STP_DELAY1 |
339 *============================================================================================*/
340 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
341
342 if(ch>3)
343 {
344 printk("[DRV] %s CHID Error\n", __func__);
345 return;
346 }
347
348 REG_SET_0x68_0_8_H_DLY_LSB( ch, param->h_delay_lsb );
349 REG_SET_0x6c_0_8_H_DLY_MSB( ch, param->h_dly_msb);
350 REG_SET_0x60_0_8_Y_DLY( ch, param->y_delay );
351 REG_SET_0x78_0_8_V_BLK_END_A( ch, param->v_blk_end_a );
352
353 REG_SET_5x38_4_1_H_MASK_ON( ch, param->h_mask_on );
354 REG_SET_5x38_0_4_H_MASK_SEL( ch, param->h_mask_sel );
355
356 REG_SET_0x64_0_8_V_BLK_END_B( ch, param->v_blk_end_b );
357 REG_SET_0x14_4_1_FLD_INV( ch, param->fld_inv );
358
359 REG_SET_5x64_0_8_MEM_RDP( ch, param->mem_rdp );
360 REG_SET_5x47_0_8_SYNC_RS( ch, param->sync_rs );
361 REG_SET_5xA9_0_8_V_BLK_END_B( ch, param->v_blk_end_b );
362
363 }
364
vd_vi_h_scaler_mode_set_seq6(unsigned char dev,unsigned char ch,void * p_param)365 static void vd_vi_h_scaler_mode_set_seq6( unsigned char dev, unsigned char ch, void *p_param )
366 {
367 /*============================================================================================
368 * Bank 5x53
369 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
370 *| | | PROTECTION_OFF | BT_601_SEL | LINEMEM_MD | | C_DITHER_ON |
371 *============================================================================================*/
372 /*============================================================================================
373 * Bank 9x96
374 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
375 *| | | | CH1_H_DOWN_SCALER_EN | | | CH1_H_SCALER_TRS_SEL | CH1_H_SCALER_ENABLE |
376 *============================================================================================*/
377 /*============================================================================================
378 * Bank 9x97
379 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
380 *| CH1_H_SCALER_MODE | CH1_H_SCALER_RD_MODE | CH1_H_SCALER_AUTO_H_REF | CH1_H_SCALER_AUTO |
381 *============================================================================================*/
382 /*============================================================================================
383 * Bank 9x98
384 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
385 *| CH1_H_SCALER_H_REF_BASE[7:0] |
386 * Bank 9x99
387 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
388 *| CH1_H_SCALER_H_REF_BASE[15:8] |
389 *============================================================================================*/
390
391 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
392
393 if(ch>3)
394 {
395 printk("[DRV] %s CHID Error\n", __func__);
396 return;
397 }
398
399 REG_SET_5x53_2_2_LINEMEM_MD( ch, param->line_mem_mode );
400
401 REG_SET_9x96_0_8_H_DOWN_SCALER( ch, param->h_down_scaler );
402 REG_SET_9x97_0_8_H_SCALER_MODE( ch, param->h_scaler_mode );
403 REG_SET_9x98_0_8_REF_BASE_LSB( ch, param->ref_base_lsb );
404 REG_SET_9x99_0_8_REF_BASE_MSB( ch, param->ref_base_msb );
405 REG_SET_9x9E_0_8_H_SCALER_OUTPUT_H_ACTIVE( ch, param->h_scaler_active );
406 }
407
vd_vi_hpll_set_seq7(unsigned char dev,unsigned char ch,void * p_param)408 static void vd_vi_hpll_set_seq7( unsigned char dev, unsigned char ch, void *p_param )
409 {
410 /*============================================================================================
411 * Bank 5x50
412 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
413 *| | NCO_GDF_COEFF_IV | | NCO_GDF_COEFF_OFF | Y_TEMP_SEL(5T,15T) | HPLL_MASK_ON | CONT_SUB |
414 *============================================================================================*/
415 /*============================================================================================
416 * Bank 5xb8
417 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
418 *| HAFC_BYPASS | HAFC_HCOEFF_SEL | HAFC_OP_MD |
419 *============================================================================================*/
420 /*============================================================================================
421 * Bank 5xbb
422 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
423 *| HPLL_MASK_END |
424 *============================================================================================*/
425 /*============================================================================================
426 * Bank 5xbb
427 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
428 *| HAFC_BYP_TH_S(write) |
429 *============================================================================================*/
430 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
431
432 if(ch>3)
433 {
434 printk("[DRV] %s CHID Error\n", __func__);
435 return;
436 }
437
438 REG_SET_5x50_0_8_HPLL_MASK_ON( ch, param->hpll_mask_on );
439 REG_SET_5xB8_0_8_HAFC_OP_MD( ch, param->hafc_op_md );
440 REG_SET_5xBB_0_8_HAFC_BYP_TH_E( ch, param->hafc_byp_th_e );
441 REG_SET_5xB7_0_8_HAFC_BYP_TH_S( ch, param->hafc_byp_th_s );
442
443 }
444
vd_vi_color_set_seq8(unsigned char dev,unsigned char ch,void * p_param,NC_VIVO_CH_FORMATDEF fmt)445 static void vd_vi_color_set_seq8( unsigned char dev, unsigned char ch, void *p_param, NC_VIVO_CH_FORMATDEF fmt )
446 {
447 /*============================================================================================
448 * gpio_i2c_write(jaguar1_i2c_addr[dev], 0x22 + (ch*4), 0x0B ); // Raptor3
449 * Bank 0x5c
450 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
451 *| PAL_CM_OFF | | | COLOROFF | C_KILL |
452 *============================================================================================*/
453 /*============================================================================================
454 * Bank 5x26
455 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
456 *| FSC_LOCK_SENSE |
457 *============================================================================================*/
458 /*============================================================================================
459 * Bank 5xb8
460 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
461 *| HAFC_BYPASS | HAFC_HCOEFF_SEL | HAFC_OP_MD |
462 *============================================================================================*/
463 /*============================================================================================
464 * Bank 9x40
465 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
466 *| FSC_DET_ | FSC_DET_ | FSC_DET_ | FSC_DET_ | FSC_DET_ | FSC_DET_ | | FSC_RST_ |
467 *| AUTO_RST1 | UNLIM1 | AUTO1 | PRESET1 | MODE1 | REFER_AUTO1 | | STRB1 |
468 *============================================================================================*/
469
470 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
471
472 REG_SET_0x20_0_8_BRIGHTNESS( ch, param->brightnees );
473 REG_SET_0x24_0_8_CONTARST( ch, param->contrast );
474 REG_SET_0x28_0_8_BLACK_LEVEL( ch, param->black_level );
475 REG_SET_0x58_0_8_SATURATION_A( ch, param->saturation_a );
476 REG_SET_0x40_0_8_HUE( ch, param->hue );
477 REG_SET_0x44_0_8_U_GAIN( ch, param->u_gain );
478 REG_SET_0x48_0_8_V_GAIN( ch, param->v_gain );
479 REG_SET_0x4C_0_8_U_OFFSET( ch, param->u_offset );
480 REG_SET_0x50_0_8_V_OFFSET( ch, param->v_offset );
481 REG_SET_5x2B_0_8_SATURATION_B( ch, param->saturation_b );
482 REG_SET_5x24_0_8_BURSET_DEC_A( ch, param->burst_dec_a );
483 REG_SET_5x5F_0_8_BURSET_DEC_B( ch, param->burst_dec_b );
484 REG_SET_5xD1_0_8_BURSET_DEC_C( ch, param->burst_dec_c );
485
486 REG_SET_9x44_0_8_FSC_EXT_EN( ch, 0x00 );
487 REG_SET_9x50_0_8_FSC_EXT_VAL_7_0( ch, 0x30 );
488 REG_SET_9x51_0_8_FSC_EXT_VAL_15_8( ch, 0x6f );
489 REG_SET_9x52_0_8_FSC_EXT_VAL_23_16( ch, 0x67 );
490 REG_SET_9x53_0_8_FSC_EXT_VAL_31_24( ch, 0x48 );
491
492 if(fmt == TVI_5M_12_5P)
493 {
494 REG_SET_5x26_0_8_FSC_LOCK_SENSE( ch, 0x20 );
495 }
496 else
497 REG_SET_5x26_0_8_FSC_LOCK_SENSE( ch, 0x40 );
498
499 if(fmt == AHD20_SD_H960_2EX_Btype_NT || fmt == AHD20_SD_H960_2EX_Btype_PAL)
500 {
501 REG_SET_5xB8_0_8_HPLL_MASK_END( ch, 0xb8 );
502 REG_SET_9x40_0_8_FSC_DET_MODE( ch, 0x00);
503 }
504 else
505 {
506 REG_SET_5xB8_0_8_HPLL_MASK_END( ch, 0x39 );
507 REG_SET_9x40_0_8_FSC_DET_MODE( ch, 0x00 );
508
509 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
510 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xb5, 0x80); // HPLL Locking Ref. Range
511 }
512
513 }
514
vd_vi_clock_set_seq9(unsigned char dev,unsigned char ch,void * p_param)515 static void vd_vi_clock_set_seq9( unsigned char dev, unsigned char ch, void *p_param )
516 {
517 /*============================================================================================
518 * Bank 1x84
519 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
520 *| VADC_CLK1_DLY_SEL | VADC_CLK1_SEL |
521 *============================================================================================*/
522 /*============================================================================================
523 * Bank 1x88
524 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
525 *| | | | | | | DEC_PRECLK |
526 * Bank 1x8c
527 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
528 *| | | | | | | DEC_POSTCLK |
529 *============================================================================================*/
530 /*============================================================================================
531 * ADC -> PRE -> POST -> VCLK
532 * ADC_CLK 1x84[3:0]
533 * 0 ~ 3 : 37.125 MHz
534 * 4 ~ 5 : 74.25 MHz
535 * 8 ~ 9 : 148.5 MHz
536 * Pre_Clock 1x88 / Post Clock 1x8C
537 * 0 : 37.125
538 * 1 : 74.25
539 * 2 : 148.5
540 * VCLK 1xCC[7:4]
541 * 4 ~ 5 : 74.25 MHz
542 * 6 ~ 7 : 148.5 MHz
543 *============================================================================================*/
544
545 NC_VD_VI_Init_STR *param = (NC_VD_VI_Init_STR*)p_param;
546
547 REG_SET_1x84_0_8_CLK_ADC( ch, param->clk_adc );
548 REG_SET_1x88_0_8_CLK_PRE( ch, param->clk_pre );
549 REG_SET_1x8c_0_8_CLK_POST( ch, param->clk_post );
550
551 REG_SET_5x01_0_8_CML_MODE( ch, param->cml_mode );
552 REG_SET_5x05_0_8_AGC_OP( ch, param->agc_op );
553 REG_SET_5x1D_0_8_G_SEL( ch, param->g_sel );
554
555 }
556
557 //==================================================================================================================
558
559 /**************************************************************************************
560 * Jaguar1 Video Output Setting Function
561 *
562 *
563 ***************************************************************************************/
vd_vo_seq_set(unsigned char dev,unsigned char ch,void * p_param)564 void vd_vo_seq_set( unsigned char dev, unsigned char ch, void *p_param )
565 {
566 /*
567 * BT656 or BT1120 Set????...
568 * */
569 NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
570
571 // BANK 1
572 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x01);
573 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc0 + (ch * 0x02), param->port_seq_ch01[ch]);
574 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc1 + (ch * 0x02), param->port_seq_ch23[ch]);
575
576 }
577
vd_vo_output_seq_set(unsigned char dev,unsigned char port,unsigned char out_ch)578 static void vd_vo_output_seq_set( unsigned char dev, unsigned char port, unsigned char out_ch )
579 {
580 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x01);
581 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc0 + (port * 0x02), out_ch);
582 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xc1 + (port * 0x02), out_ch);
583 }
584
vd_vo_port_y_c_merge_set(unsigned char dev,unsigned char ch,void * p_param)585 static void vd_vo_port_y_c_merge_set( unsigned char dev, unsigned char ch, void *p_param)
586 {
587 NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
588
589 /*============================================================================================
590 * Address: 1xec
591 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
592 *| | | | | | | | MUX_YC_MERGE1 |
593 *============================================================================================*/
594 REG_SET_1xEC_0_8_yc_merge( ch, param->mux_yc_merge );
595
596 }
597
vd_vo_port_ch_id_set(unsigned char dev,unsigned char ch,void * p_param)598 static void vd_vo_port_ch_id_set( unsigned char dev, unsigned char ch, void *p_param )
599 {
600 NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
601 unsigned char val_0x14 = 0x00;
602
603 /*============================================================================================
604 * Address: 0x14
605 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
606 *| | | | FLD_INV_1 | CHID_VIN1 |
607 *============================================================================================*/
608 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x00);
609 val_0x14 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x14 + ch);
610 val_0x14 = val_0x14 & 0x10;
611 val_0x14 = val_0x14 | param->chid_vin;
612 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + ch, val_0x14);
613
614 }
615
vd_vo_mux_mode_set(unsigned char dev,unsigned char ch,void * p_param)616 static void vd_vo_mux_mode_set( unsigned char dev, unsigned char ch, void *p_param )
617 {
618 NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
619
620 /*============================================================================================
621 * Address: 1xc8
622 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
623 *| | | VCLK_1_EN | VDO_1_EN | VPORT_1_CH_OUT_SEL |
624 *============================================================================================*/
625 REG_SET_1xC8_0_8_out_sel( ch , param->vport_out_sel );
626
627 }
628
vd_vo_manual_mode_set(unsigned char dev,unsigned char ch,void * p_param)629 static void vd_vo_manual_mode_set(unsigned char dev, unsigned char ch, void *p_param )
630 {
631 //NC_VD_VO_Init_STR *param = (NC_VD_VO_Init_STR*)p_param;
632
633 unsigned char val_0x30;
634 unsigned char val_0x31;
635 unsigned char val_0x32;
636
637 /*============================================================================================
638 * Address: 13x30
639 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
640 *| | | | | NOVIDEO_VFC_INIT_EN[3:0] | | | |
641 *============================================================================================*/
642 /*============================================================================================
643 * Address: 13x31
644 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
645 *| | | AHD_8M_det_en | AHD_5M_det_en | AHD_4M_det_en | AHD_3M_det_en | AHD_2M_det_en | AHD_1M_det_en |
646 *============================================================================================*/
647 /*============================================================================================
648 * Address: 13x32
649 *| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
650 *| | | CVI_8M_det_en | CVI_5M_det_en | CVI_4M_det_en | CVI_3M_det_en | CVI_2M_det_en | CVI_1M_det_en |
651 *============================================================================================*/
652
653 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xFF, 0x13);
654 val_0x30 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x30);
655 val_0x31 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x31);
656 val_0x32 = gpio_i2c_read(jaguar1_i2c_addr[dev], 0x32);
657
658 val_0x30 &= (~(1 << (ch + 4)) & (~(1 << ch)));
659 val_0x31 &= (~(1 << (ch + 4)) & (~(1 << ch)));
660 val_0x32 &= (~(1 << ch));
661
662 // 0x00 Set Test
663 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x30, val_0x30);
664 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x31, val_0x31);
665 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x32, val_0x32);
666
667 }
668
vd_jaguar1_single_differ_set(unsigned char dev,unsigned char ch,int input)669 static void vd_jaguar1_single_differ_set( unsigned char dev, unsigned char ch, int input )
670 {
671 REG_SET_0x18_0_8_EX_CBAR_ON( ch, 0x13 );
672
673 if( input == DIFFERENTIAL )
674 {
675 REG_SET_5x00_0_8_CMP( ch, 0xd0 );
676 REG_SET_5x01_0_8_CML( ch, 0x2c );
677 REG_SET_5x1D_0_8_AFE( ch, 0x8c );
678 REG_SET_5x92_0_8_PWM( ch, 0x00 );
679 }
680 else if( input == SINGLE_ENDED )
681 {
682 REG_SET_5x00_0_8_CMP( ch, 0xd0 );
683 REG_SET_5x01_0_8_CML( ch, 0xa2 );
684 //REG_SET_5x1D_0_8_AFE( ch, 0x00 );
685 REG_SET_5x92_0_8_PWM( ch, 0x00 );
686 }
687 else
688 {
689 printk("Jaguar1 Analog Input Setting Fail !!!\n");
690 }
691
692 }
693
vd_jaguar1_960p_30P_test_set(unsigned char dev,unsigned char ch)694 static void vd_jaguar1_960p_30P_test_set( unsigned char dev, unsigned char ch )
695 {
696 printk("[drv]vd_jaguar1_960p_30P_test_set >>> ch%d!!\n", ch);
697 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x00);
698 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x68 + ch, 0x4E);
699 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x69 + ch, 0x80);
700 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6a + ch, 0x80);
701 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6b + ch, 0x80);
702 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ch, 0x00);
703 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x08 + ch, 0x02);
704 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ch, 0x00);
705 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x18 + ch, 0x01);
706 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x64 + ch, 0x06);
707
708 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x01);
709 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x84 + ch, 0x04);
710 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x88 + ch, 0x01);
711 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x8c + ch, 0x02);
712
713 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
714 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6e, 0x10);
715 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6f, 0x82);
716 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x76, 0x00);
717 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x77, 0x80);
718 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x78, 0x00);
719 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x79, 0x11);
720 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xB5, 0x80);
721
722 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x11);
723 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x00 + ( ch * 0x20 ), 0x0f);
724 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x01 + ( ch * 0x20 ), 0x00);
725 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x02 + ( ch * 0x20 ), 0x9d);
726 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x03 + ( ch * 0x20 ), 0x05);
727 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ( ch * 0x20 ), 0x00);
728 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x05 + ( ch * 0x20 ), 0x08);
729 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x06 + ( ch * 0x20 ), 0xca);
730 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0a + ( ch * 0x20 ), 0x03);
731 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0b + ( ch * 0x20 ), 0xc0);
732 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ( ch * 0x20 ), 0x04);
733 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0d + ( ch * 0x20 ), 0x4b);
734 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x10 + ( ch * 0x20 ), 0x00);
735 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x11 + ( ch * 0x20 ), 0x96);
736 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x12 + ( ch * 0x20 ), 0x00);
737 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x13 + ( ch * 0x20 ), 0x82);
738 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + ( ch * 0x20 ), 0x00);
739 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x15 + ( ch * 0x20 ), 0x30);
740
741 }
742
vd_jaguar1_960p_25P_test_set(unsigned char dev,unsigned char ch)743 static void vd_jaguar1_960p_25P_test_set( unsigned char dev, unsigned char ch )
744 {
745 printk("[drv]vd_jaguar1_960p_25P_test_set >>> ch%d!!\n", ch);
746 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x00);
747 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x68 + ch, 0x59);
748 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x69 + ch, 0x80);
749 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6a + ch, 0x80);
750 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6b + ch, 0x80);
751 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ch, 0x00);
752 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x08 + ch, 0x03);
753 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ch, 0x00);
754 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x18 + ch, 0x01);
755 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x64 + ch, 0x06);
756
757 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x01);
758 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x84 + ch, 0x04);
759 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x88 + ch, 0x01);
760 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x8c + ch, 0x02);
761
762 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x05 + ch);
763 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6e, 0x10);
764 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x6f, 0x82);
765 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x76, 0x00);
766 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x77, 0x80);
767 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x78, 0x00);
768 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x79, 0x11);
769 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xB5, 0x80);
770
771 // Only AHD20_720P_960P_25P
772 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x09);
773 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x53 + (ch * 0x04), 0x52);
774 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x52 + (ch * 0x04), 0xd2);
775 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x51 + (ch * 0x04), 0x1c);
776 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x50 + (ch * 0x04), 0x10);
777 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x44 + ch, 0x01);
778
779 gpio_i2c_write(jaguar1_i2c_addr[dev], 0xff, 0x11);
780 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x00 + ( ch * 0x20 ), 0x0f);
781 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x01 + ( ch * 0x20 ), 0x00);
782 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x02 + ( ch * 0x20 ), 0x97);
783 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x03 + ( ch * 0x20 ), 0x05);
784 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x04 + ( ch * 0x20 ), 0x00);
785 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x05 + ( ch * 0x20 ), 0x0a);
786 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x06 + ( ch * 0x20 ), 0x8c);
787 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0a + ( ch * 0x20 ), 0x03);
788 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0b + ( ch * 0x20 ), 0xc0);
789 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0c + ( ch * 0x20 ), 0x04);
790 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x0d + ( ch * 0x20 ), 0x4c);
791 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x10 + ( ch * 0x20 ), 0x00);
792 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x11 + ( ch * 0x20 ), 0x96);
793 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x12 + ( ch * 0x20 ), 0x00);
794 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x13 + ( ch * 0x20 ), 0x82);
795 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x14 + ( ch * 0x20 ), 0x00);
796 gpio_i2c_write(jaguar1_i2c_addr[dev], 0x15 + ( ch * 0x20 ), 0x30);
797
798 }
799
800 /*****************************************************************************************************************************************
801 * Jaguar1 Video ioctl function
802 * video vi_vo initialize
803 *
804 ******************************************************************************************************************************************/
vd_jaguar1_vo_ch_seq_set(void * p_param)805 void vd_jaguar1_vo_ch_seq_set( void *p_param)
806 {
807 video_output_init *vo_seq = (video_output_init*)p_param;
808 unsigned char dev = 0;
809 unsigned char port = vo_seq->port;
810 unsigned char out_ch = vo_seq->out_ch;
811
812 vd_vo_output_seq_set( dev, port, out_ch );
813 }
814
vd_jaguar1_init_set(void * p_param)815 void vd_jaguar1_init_set( void *p_param )
816 {
817 video_input_init *video_init = (video_input_init*)p_param;
818 unsigned char ch = video_init->ch % 4;
819 unsigned char fmt = video_init->format;
820 int analog_input = video_init->input;
821
822 video_equalizer_info_s eq_set;
823 NC_VD_COAX_STR coax_init;
824 NC_VD_VI_Init_STR *vi_param;
825 NC_VD_VO_Init_STR *vo_param;
826
827 int dev = ch / 4 ; //{0x64, 0x60, 0x62, 0x66}//
828
829 vi_param = __NC_VD_VI_Init_Val_Get(fmt);
830 vo_param = __NC_VD_VO_Init_Val_Get(AHD20_1080P_30P);
831
832 // Each_Mode_Set
833 REG_SET_0x00_0_8_EACH_SET(ch, 0x10);
834 /*=====================================================
835 * vd_Analog Input Setting
836 *=====================================================*/
837 vd_jaguar1_single_differ_set(dev, ch, analog_input);
838
839 /*=====================================================
840 * vd_vo Setting
841 *=====================================================*/
842 vd_vo_port_y_c_merge_set( dev, ch, vo_param );
843 vd_vo_mux_mode_set( dev, ch, vo_param );
844 vd_vo_manual_mode_set(dev, ch, vo_param);
845
846 /*=====================================================
847 * vd_vi Setting
848 *=====================================================*/
849
850 vd_vi_manual_set_seq1( dev, ch, vi_param );
851 vd_vi_vafe_set_seq2( dev, ch );
852 vd_vi_format_set_seq3( dev, ch, vi_param );
853 vd_vi_chroma_set_seq4( dev, ch, vi_param );
854 vd_vi_h_timing_set_seq5( dev, ch, vi_param );
855 vd_vi_h_scaler_mode_set_seq6( dev, ch, vi_param );
856
857 vd_vi_hpll_set_seq7( dev, ch, vi_param );
858 vd_vi_color_set_seq8( dev, ch, vi_param, fmt);
859 vd_vo_port_ch_id_set( dev, ch, vo_param );
860 vd_vi_clock_set_seq9( dev, ch, vi_param );
861
862 /*=====================================================
863 * AHD 1280x960P Test
864 *
865 *=====================================================*/
866 if( fmt == AHD20_720P_960P_30P )
867 {
868 vd_jaguar1_960p_30P_test_set( 0, ch);
869 current_bank_set(0xFF);
870 }
871 else if( fmt == AHD20_720P_960P_25P)
872 {
873 vd_jaguar1_960p_25P_test_set( 0, ch);
874 current_bank_set(0xFF);
875 }
876 else if( fmt == AHD20_SD_H960_2EX_Btype_PAL )
877 {
878 REG_SET_0x70_0_8_V_DELAY( ch, 0x3F );
879 }
880 else if( fmt == AHD20_SD_SH720_PAL || fmt == AHD20_SD_SH720_NT || fmt == AHD20_SD_H1440_PAL || fmt == AHD20_SD_H1440_NT )
881 {
882 REG_SET_0x14_0_8_FLD_INV_CHID(ch, 0x00);
883 REG_SET_0x34_0_8_Y_FIR_MODE(ch, 0x00);
884 REG_SET_1xCC_0_8_VPORT_OCLK_SEL_VPORT_OVCLK_DLY_SEL(ch, 0x40);
885 REG_SET_1xA0_0_8_TM_CLK_EN_SET(ch, 0x10);
886 REG_SET_5x21_0_8_CONT_SUB(ch, 0x24);
887 REG_SET_5x55_0_8_C_MEM_CLK_SEL(ch, 0x00);
888 REG_SET_5x56_0_8_FREQ_MEM_CLK_SEL(ch, 0x00);
889 REG_SET_5x57_0_8_LINE_MEM_CLK_INV(ch, 0x00);
890 REG_SET_5xB5_0_8_HAFC_MASK_SEL(ch, 0x00);
891 REG_SET_5xB8_0_8_HAFC_HCOEFF_SEL(ch, 0x39);
892 REG_SET_0x7C_0_8_HZOOM(ch, 0x8F);
893 }
894 else
895 printk("\n");
896
897 printk("[drv_vi]ch::%d >>> fmt::%s\n", ch, vi_param->name);
898
899 /*=====================================================
900 * EQ Stage 0 Setting
901 *
902 *=====================================================*/
903 #if 1
904 eq_set.Ch = ch;
905 eq_set.FmtDef = fmt;
906 eq_set.Cable = CABLE_A;
907 eq_set.Input = SINGLE_ENDED;
908 eq_set.stage = STAGE_0;
909 video_input_eq_val_set( &eq_set );
910 #endif
911
912 printk("[drv_vi]ch::%d >>> fmt::%s\n", ch, vi_param->name);
913 current_bank_set(0xFF);
914
915 /*=====================================================
916 * Coaxial Initialize
917 *
918 *=====================================================*/
919 coax_init.ch = ch;
920 coax_init.vivo_fmt = fmt;
921 coax_init.vd_dev = dev;
922 coax_tx_init( &coax_init );
923 if(acp_mode_enable == 0)
924 coax_tx_16bit_init( &coax_init );
925 coax_rx_init( &coax_init );
926
927 }
928
vd_jaguar1_get_novideo(video_video_loss_s * vidloss)929 void vd_jaguar1_get_novideo( video_video_loss_s *vidloss )
930 {
931 gpio_i2c_write(jaguar1_i2c_addr[vidloss->devnum], 0xFF, 0x00);
932 vidloss->videoloss = gpio_i2c_read(jaguar1_i2c_addr[vidloss->devnum], 0xA0);
933 }
934
vd_jaguar1_sw_reset(void * p_param)935 void vd_jaguar1_sw_reset( void *p_param )
936 {
937 //video_input_init *sw_rst = (video_input_init*)p_param;
938
939 REG_SET_1x81_0_1_VPLL_RST( 0, 0x1 );
940 REG_SET_1x80_0_1_VPLL_C( 0, 0x1 );
941 REG_SET_1x80_0_1_VPLL_C( 0, 0x0 );
942 REG_SET_1x81_0_1_VPLL_RST( 0, 0x0 );
943 printk("[drv]jaguar1_sw_reset complete!!\n");
944 }
945
946