Searched refs:REG_SET_1x81_0_1_VPLL_RST (Results 1 – 2 of 2) sorted by relevance
939 REG_SET_1x81_0_1_VPLL_RST( 0, 0x1 ); in vd_jaguar1_sw_reset()942 REG_SET_1x81_0_1_VPLL_RST( 0, 0x0 ); in vd_jaguar1_sw_reset()
153 #define REG_SET_1x81_0_1_VPLL_RST(ch, val) vd_register_set ( 0 , 0x01 , 0x81 , val , 0 , 1 ) macro