Searched refs:REG_SET_0x6c_0_8_H_DLY_MSB (Results 1 – 2 of 2) sorted by relevance
92 #define REG_SET_0x6c_0_8_H_DLY_MSB(ch, val) vd_register_set ( 0 , 0x00 , 0x6c + ch , val , 0 , 8 ) macro
349 REG_SET_0x6c_0_8_H_DLY_MSB( ch, param->h_dly_msb); in vd_vi_h_timing_set_seq5()