Searched refs:PPLL_DIV_3 (Results 1 – 6 of 6) sorted by relevance
216 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()265 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()266 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
248 #define PPLL_DIV_3 0x0007 macro
435 #define PPLL_DIV_3 0x0007 macro
1341 save->ppll_div_3 = INPLL(PPLL_DIV_3); in radeon_save_state()1362 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()1411 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()1412 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
1339 div3 = aty_ld_pll(PPLL_DIV_3); in aty128_set_pll()1347 aty_st_pll(PPLL_DIV_3, div3); in aty128_set_pll()
437 #define PPLL_DIV_3 0x0007 macro