1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $ 3*4882a593Smuzhiyun * linux/drivers/video/aty128.h 4*4882a593Smuzhiyun * Register definitions for ATI Rage128 boards 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Anthony Tong <atong@uiuc.edu>, 1999 7*4882a593Smuzhiyun * Brad Douglas <brad@neruo.com>, 2000 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef REG_RAGE128_H 11*4882a593Smuzhiyun #define REG_RAGE128_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CLOCK_CNTL_INDEX 0x0008 14*4882a593Smuzhiyun #define CLOCK_CNTL_DATA 0x000c 15*4882a593Smuzhiyun #define BIOS_0_SCRATCH 0x0010 16*4882a593Smuzhiyun #define BUS_CNTL 0x0030 17*4882a593Smuzhiyun #define BUS_CNTL1 0x0034 18*4882a593Smuzhiyun #define GEN_INT_CNTL 0x0040 19*4882a593Smuzhiyun #define CRTC_GEN_CNTL 0x0050 20*4882a593Smuzhiyun #define CRTC_EXT_CNTL 0x0054 21*4882a593Smuzhiyun #define DAC_CNTL 0x0058 22*4882a593Smuzhiyun #define I2C_CNTL_1 0x0094 23*4882a593Smuzhiyun #define PALETTE_INDEX 0x00b0 24*4882a593Smuzhiyun #define PALETTE_DATA 0x00b4 25*4882a593Smuzhiyun #define CNFG_CNTL 0x00e0 26*4882a593Smuzhiyun #define GEN_RESET_CNTL 0x00f0 27*4882a593Smuzhiyun #define CNFG_MEMSIZE 0x00f8 28*4882a593Smuzhiyun #define MEM_CNTL 0x0140 29*4882a593Smuzhiyun #define MEM_POWER_MISC 0x015c 30*4882a593Smuzhiyun #define AGP_BASE 0x0170 31*4882a593Smuzhiyun #define AGP_CNTL 0x0174 32*4882a593Smuzhiyun #define AGP_APER_OFFSET 0x0178 33*4882a593Smuzhiyun #define PCI_GART_PAGE 0x017c 34*4882a593Smuzhiyun #define PC_NGUI_MODE 0x0180 35*4882a593Smuzhiyun #define PC_NGUI_CTLSTAT 0x0184 36*4882a593Smuzhiyun #define MPP_TB_CONFIG 0x01C0 37*4882a593Smuzhiyun #define MPP_GP_CONFIG 0x01C8 38*4882a593Smuzhiyun #define VIPH_CONTROL 0x01D0 39*4882a593Smuzhiyun #define CRTC_H_TOTAL_DISP 0x0200 40*4882a593Smuzhiyun #define CRTC_H_SYNC_STRT_WID 0x0204 41*4882a593Smuzhiyun #define CRTC_V_TOTAL_DISP 0x0208 42*4882a593Smuzhiyun #define CRTC_V_SYNC_STRT_WID 0x020c 43*4882a593Smuzhiyun #define CRTC_VLINE_CRNT_VLINE 0x0210 44*4882a593Smuzhiyun #define CRTC_CRNT_FRAME 0x0214 45*4882a593Smuzhiyun #define CRTC_GUI_TRIG_VLINE 0x0218 46*4882a593Smuzhiyun #define CRTC_OFFSET 0x0224 47*4882a593Smuzhiyun #define CRTC_OFFSET_CNTL 0x0228 48*4882a593Smuzhiyun #define CRTC_PITCH 0x022c 49*4882a593Smuzhiyun #define OVR_CLR 0x0230 50*4882a593Smuzhiyun #define OVR_WID_LEFT_RIGHT 0x0234 51*4882a593Smuzhiyun #define OVR_WID_TOP_BOTTOM 0x0238 52*4882a593Smuzhiyun #define LVDS_GEN_CNTL 0x02d0 53*4882a593Smuzhiyun #define DDA_CONFIG 0x02e0 54*4882a593Smuzhiyun #define DDA_ON_OFF 0x02e4 55*4882a593Smuzhiyun #define VGA_DDA_CONFIG 0x02e8 56*4882a593Smuzhiyun #define VGA_DDA_ON_OFF 0x02ec 57*4882a593Smuzhiyun #define CRTC2_H_TOTAL_DISP 0x0300 58*4882a593Smuzhiyun #define CRTC2_H_SYNC_STRT_WID 0x0304 59*4882a593Smuzhiyun #define CRTC2_V_TOTAL_DISP 0x0308 60*4882a593Smuzhiyun #define CRTC2_V_SYNC_STRT_WID 0x030c 61*4882a593Smuzhiyun #define CRTC2_VLINE_CRNT_VLINE 0x0310 62*4882a593Smuzhiyun #define CRTC2_CRNT_FRAME 0x0314 63*4882a593Smuzhiyun #define CRTC2_GUI_TRIG_VLINE 0x0318 64*4882a593Smuzhiyun #define CRTC2_OFFSET 0x0324 65*4882a593Smuzhiyun #define CRTC2_OFFSET_CNTL 0x0328 66*4882a593Smuzhiyun #define CRTC2_PITCH 0x032c 67*4882a593Smuzhiyun #define DDA2_CONFIG 0x03e0 68*4882a593Smuzhiyun #define DDA2_ON_OFF 0x03e4 69*4882a593Smuzhiyun #define CRTC2_GEN_CNTL 0x03f8 70*4882a593Smuzhiyun #define CRTC2_STATUS 0x03fc 71*4882a593Smuzhiyun #define OV0_SCALE_CNTL 0x0420 72*4882a593Smuzhiyun #define SUBPIC_CNTL 0x0540 73*4882a593Smuzhiyun #define PM4_BUFFER_OFFSET 0x0700 74*4882a593Smuzhiyun #define PM4_BUFFER_CNTL 0x0704 75*4882a593Smuzhiyun #define PM4_BUFFER_WM_CNTL 0x0708 76*4882a593Smuzhiyun #define PM4_BUFFER_DL_RPTR_ADDR 0x070c 77*4882a593Smuzhiyun #define PM4_BUFFER_DL_RPTR 0x0710 78*4882a593Smuzhiyun #define PM4_BUFFER_DL_WPTR 0x0714 79*4882a593Smuzhiyun #define PM4_VC_FPU_SETUP 0x071c 80*4882a593Smuzhiyun #define PM4_FPU_CNTL 0x0720 81*4882a593Smuzhiyun #define PM4_VC_FORMAT 0x0724 82*4882a593Smuzhiyun #define PM4_VC_CNTL 0x0728 83*4882a593Smuzhiyun #define PM4_VC_I01 0x072c 84*4882a593Smuzhiyun #define PM4_VC_VLOFF 0x0730 85*4882a593Smuzhiyun #define PM4_VC_VLSIZE 0x0734 86*4882a593Smuzhiyun #define PM4_IW_INDOFF 0x0738 87*4882a593Smuzhiyun #define PM4_IW_INDSIZE 0x073c 88*4882a593Smuzhiyun #define PM4_FPU_FPX0 0x0740 89*4882a593Smuzhiyun #define PM4_FPU_FPY0 0x0744 90*4882a593Smuzhiyun #define PM4_FPU_FPX1 0x0748 91*4882a593Smuzhiyun #define PM4_FPU_FPY1 0x074c 92*4882a593Smuzhiyun #define PM4_FPU_FPX2 0x0750 93*4882a593Smuzhiyun #define PM4_FPU_FPY2 0x0754 94*4882a593Smuzhiyun #define PM4_FPU_FPY3 0x0758 95*4882a593Smuzhiyun #define PM4_FPU_FPY4 0x075c 96*4882a593Smuzhiyun #define PM4_FPU_FPY5 0x0760 97*4882a593Smuzhiyun #define PM4_FPU_FPY6 0x0764 98*4882a593Smuzhiyun #define PM4_FPU_FPR 0x0768 99*4882a593Smuzhiyun #define PM4_FPU_FPG 0x076c 100*4882a593Smuzhiyun #define PM4_FPU_FPB 0x0770 101*4882a593Smuzhiyun #define PM4_FPU_FPA 0x0774 102*4882a593Smuzhiyun #define PM4_FPU_INTXY0 0x0780 103*4882a593Smuzhiyun #define PM4_FPU_INTXY1 0x0784 104*4882a593Smuzhiyun #define PM4_FPU_INTXY2 0x0788 105*4882a593Smuzhiyun #define PM4_FPU_INTARGB 0x078c 106*4882a593Smuzhiyun #define PM4_FPU_FPTWICEAREA 0x0790 107*4882a593Smuzhiyun #define PM4_FPU_DMAJOR01 0x0794 108*4882a593Smuzhiyun #define PM4_FPU_DMAJOR12 0x0798 109*4882a593Smuzhiyun #define PM4_FPU_DMAJOR02 0x079c 110*4882a593Smuzhiyun #define PM4_FPU_STAT 0x07a0 111*4882a593Smuzhiyun #define PM4_STAT 0x07b8 112*4882a593Smuzhiyun #define PM4_TEST_CNTL 0x07d0 113*4882a593Smuzhiyun #define PM4_MICROCODE_ADDR 0x07d4 114*4882a593Smuzhiyun #define PM4_MICROCODE_RADDR 0x07d8 115*4882a593Smuzhiyun #define PM4_MICROCODE_DATAH 0x07dc 116*4882a593Smuzhiyun #define PM4_MICROCODE_DATAL 0x07e0 117*4882a593Smuzhiyun #define PM4_CMDFIFO_ADDR 0x07e4 118*4882a593Smuzhiyun #define PM4_CMDFIFO_DATAH 0x07e8 119*4882a593Smuzhiyun #define PM4_CMDFIFO_DATAL 0x07ec 120*4882a593Smuzhiyun #define PM4_BUFFER_ADDR 0x07f0 121*4882a593Smuzhiyun #define PM4_BUFFER_DATAH 0x07f4 122*4882a593Smuzhiyun #define PM4_BUFFER_DATAL 0x07f8 123*4882a593Smuzhiyun #define PM4_MICRO_CNTL 0x07fc 124*4882a593Smuzhiyun #define CAP0_TRIG_CNTL 0x0950 125*4882a593Smuzhiyun #define CAP1_TRIG_CNTL 0x09c0 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /****************************************************************************** 128*4882a593Smuzhiyun * GUI Block Memory Mapped Registers * 129*4882a593Smuzhiyun * These registers are FIFOed. * 130*4882a593Smuzhiyun *****************************************************************************/ 131*4882a593Smuzhiyun #define PM4_FIFO_DATA_EVEN 0x1000 132*4882a593Smuzhiyun #define PM4_FIFO_DATA_ODD 0x1004 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define DST_OFFSET 0x1404 135*4882a593Smuzhiyun #define DST_PITCH 0x1408 136*4882a593Smuzhiyun #define DST_WIDTH 0x140c 137*4882a593Smuzhiyun #define DST_HEIGHT 0x1410 138*4882a593Smuzhiyun #define SRC_X 0x1414 139*4882a593Smuzhiyun #define SRC_Y 0x1418 140*4882a593Smuzhiyun #define DST_X 0x141c 141*4882a593Smuzhiyun #define DST_Y 0x1420 142*4882a593Smuzhiyun #define SRC_PITCH_OFFSET 0x1428 143*4882a593Smuzhiyun #define DST_PITCH_OFFSET 0x142c 144*4882a593Smuzhiyun #define SRC_Y_X 0x1434 145*4882a593Smuzhiyun #define DST_Y_X 0x1438 146*4882a593Smuzhiyun #define DST_HEIGHT_WIDTH 0x143c 147*4882a593Smuzhiyun #define DP_GUI_MASTER_CNTL 0x146c 148*4882a593Smuzhiyun #define BRUSH_SCALE 0x1470 149*4882a593Smuzhiyun #define BRUSH_Y_X 0x1474 150*4882a593Smuzhiyun #define DP_BRUSH_BKGD_CLR 0x1478 151*4882a593Smuzhiyun #define DP_BRUSH_FRGD_CLR 0x147c 152*4882a593Smuzhiyun #define DST_WIDTH_X 0x1588 153*4882a593Smuzhiyun #define DST_HEIGHT_WIDTH_8 0x158c 154*4882a593Smuzhiyun #define SRC_X_Y 0x1590 155*4882a593Smuzhiyun #define DST_X_Y 0x1594 156*4882a593Smuzhiyun #define DST_WIDTH_HEIGHT 0x1598 157*4882a593Smuzhiyun #define DST_WIDTH_X_INCY 0x159c 158*4882a593Smuzhiyun #define DST_HEIGHT_Y 0x15a0 159*4882a593Smuzhiyun #define DST_X_SUB 0x15a4 160*4882a593Smuzhiyun #define DST_Y_SUB 0x15a8 161*4882a593Smuzhiyun #define SRC_OFFSET 0x15ac 162*4882a593Smuzhiyun #define SRC_PITCH 0x15b0 163*4882a593Smuzhiyun #define DST_HEIGHT_WIDTH_BW 0x15b4 164*4882a593Smuzhiyun #define CLR_CMP_CNTL 0x15c0 165*4882a593Smuzhiyun #define CLR_CMP_CLR_SRC 0x15c4 166*4882a593Smuzhiyun #define CLR_CMP_CLR_DST 0x15c8 167*4882a593Smuzhiyun #define CLR_CMP_MASK 0x15cc 168*4882a593Smuzhiyun #define DP_SRC_FRGD_CLR 0x15d8 169*4882a593Smuzhiyun #define DP_SRC_BKGD_CLR 0x15dc 170*4882a593Smuzhiyun #define DST_BRES_ERR 0x1628 171*4882a593Smuzhiyun #define DST_BRES_INC 0x162c 172*4882a593Smuzhiyun #define DST_BRES_DEC 0x1630 173*4882a593Smuzhiyun #define DST_BRES_LNTH 0x1634 174*4882a593Smuzhiyun #define DST_BRES_LNTH_SUB 0x1638 175*4882a593Smuzhiyun #define SC_LEFT 0x1640 176*4882a593Smuzhiyun #define SC_RIGHT 0x1644 177*4882a593Smuzhiyun #define SC_TOP 0x1648 178*4882a593Smuzhiyun #define SC_BOTTOM 0x164c 179*4882a593Smuzhiyun #define SRC_SC_RIGHT 0x1654 180*4882a593Smuzhiyun #define SRC_SC_BOTTOM 0x165c 181*4882a593Smuzhiyun #define GUI_DEBUG0 0x16a0 182*4882a593Smuzhiyun #define GUI_DEBUG1 0x16a4 183*4882a593Smuzhiyun #define GUI_TIMEOUT 0x16b0 184*4882a593Smuzhiyun #define GUI_TIMEOUT0 0x16b4 185*4882a593Smuzhiyun #define GUI_TIMEOUT1 0x16b8 186*4882a593Smuzhiyun #define GUI_PROBE 0x16bc 187*4882a593Smuzhiyun #define DP_CNTL 0x16c0 188*4882a593Smuzhiyun #define DP_DATATYPE 0x16c4 189*4882a593Smuzhiyun #define DP_MIX 0x16c8 190*4882a593Smuzhiyun #define DP_WRITE_MASK 0x16cc 191*4882a593Smuzhiyun #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 192*4882a593Smuzhiyun #define DEFAULT_OFFSET 0x16e0 193*4882a593Smuzhiyun #define DEFAULT_PITCH 0x16e4 194*4882a593Smuzhiyun #define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 195*4882a593Smuzhiyun #define SC_TOP_LEFT 0x16ec 196*4882a593Smuzhiyun #define SC_BOTTOM_RIGHT 0x16f0 197*4882a593Smuzhiyun #define SRC_SC_BOTTOM_RIGHT 0x16f4 198*4882a593Smuzhiyun #define WAIT_UNTIL 0x1720 199*4882a593Smuzhiyun #define CACHE_CNTL 0x1724 200*4882a593Smuzhiyun #define GUI_STAT 0x1740 201*4882a593Smuzhiyun #define PC_GUI_MODE 0x1744 202*4882a593Smuzhiyun #define PC_GUI_CTLSTAT 0x1748 203*4882a593Smuzhiyun #define PC_DEBUG_MODE 0x1760 204*4882a593Smuzhiyun #define BRES_DST_ERR_DEC 0x1780 205*4882a593Smuzhiyun #define TRAIL_BRES_T12_ERR_DEC 0x1784 206*4882a593Smuzhiyun #define TRAIL_BRES_T12_INC 0x1788 207*4882a593Smuzhiyun #define DP_T12_CNTL 0x178c 208*4882a593Smuzhiyun #define DST_BRES_T1_LNTH 0x1790 209*4882a593Smuzhiyun #define DST_BRES_T2_LNTH 0x1794 210*4882a593Smuzhiyun #define SCALE_SRC_HEIGHT_WIDTH 0x1994 211*4882a593Smuzhiyun #define SCALE_OFFSET_0 0x1998 212*4882a593Smuzhiyun #define SCALE_PITCH 0x199c 213*4882a593Smuzhiyun #define SCALE_X_INC 0x19a0 214*4882a593Smuzhiyun #define SCALE_Y_INC 0x19a4 215*4882a593Smuzhiyun #define SCALE_HACC 0x19a8 216*4882a593Smuzhiyun #define SCALE_VACC 0x19ac 217*4882a593Smuzhiyun #define SCALE_DST_X_Y 0x19b0 218*4882a593Smuzhiyun #define SCALE_DST_HEIGHT_WIDTH 0x19b4 219*4882a593Smuzhiyun #define SCALE_3D_CNTL 0x1a00 220*4882a593Smuzhiyun #define SCALE_3D_DATATYPE 0x1a20 221*4882a593Smuzhiyun #define SETUP_CNTL 0x1bc4 222*4882a593Smuzhiyun #define SOLID_COLOR 0x1bc8 223*4882a593Smuzhiyun #define WINDOW_XY_OFFSET 0x1bcc 224*4882a593Smuzhiyun #define DRAW_LINE_POINT 0x1bd0 225*4882a593Smuzhiyun #define SETUP_CNTL_PM4 0x1bd4 226*4882a593Smuzhiyun #define DST_PITCH_OFFSET_C 0x1c80 227*4882a593Smuzhiyun #define DP_GUI_MASTER_CNTL_C 0x1c84 228*4882a593Smuzhiyun #define SC_TOP_LEFT_C 0x1c88 229*4882a593Smuzhiyun #define SC_BOTTOM_RIGHT_C 0x1c8c 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define CLR_CMP_MASK_3D 0x1A28 232*4882a593Smuzhiyun #define MISC_3D_STATE_CNTL_REG 0x1CA0 233*4882a593Smuzhiyun #define MC_SRC1_CNTL 0x19D8 234*4882a593Smuzhiyun #define TEX_CNTL 0x1800 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* CONSTANTS */ 237*4882a593Smuzhiyun #define GUI_ACTIVE 0x80000000 238*4882a593Smuzhiyun #define ENGINE_IDLE 0x0 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define PLL_WR_EN 0x00000080 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define CLK_PIN_CNTL 0x0001 243*4882a593Smuzhiyun #define PPLL_CNTL 0x0002 244*4882a593Smuzhiyun #define PPLL_REF_DIV 0x0003 245*4882a593Smuzhiyun #define PPLL_DIV_0 0x0004 246*4882a593Smuzhiyun #define PPLL_DIV_1 0x0005 247*4882a593Smuzhiyun #define PPLL_DIV_2 0x0006 248*4882a593Smuzhiyun #define PPLL_DIV_3 0x0007 249*4882a593Smuzhiyun #define VCLK_ECP_CNTL 0x0008 250*4882a593Smuzhiyun #define HTOTAL_CNTL 0x0009 251*4882a593Smuzhiyun #define X_MPLL_REF_FB_DIV 0x000a 252*4882a593Smuzhiyun #define XPLL_CNTL 0x000b 253*4882a593Smuzhiyun #define XDLL_CNTL 0x000c 254*4882a593Smuzhiyun #define XCLK_CNTL 0x000d 255*4882a593Smuzhiyun #define MPLL_CNTL 0x000e 256*4882a593Smuzhiyun #define MCLK_CNTL 0x000f 257*4882a593Smuzhiyun #define AGP_PLL_CNTL 0x0010 258*4882a593Smuzhiyun #define FCP_CNTL 0x0012 259*4882a593Smuzhiyun #define PLL_TEST_CNTL 0x0013 260*4882a593Smuzhiyun #define P2PLL_CNTL 0x002a 261*4882a593Smuzhiyun #define P2PLL_REF_DIV 0x002b 262*4882a593Smuzhiyun #define P2PLL_DIV_0 0x002b 263*4882a593Smuzhiyun #define POWER_MANAGEMENT 0x002f 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun #define PPLL_RESET 0x01 266*4882a593Smuzhiyun #define PPLL_ATOMIC_UPDATE_EN 0x10000 267*4882a593Smuzhiyun #define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000 268*4882a593Smuzhiyun #define PPLL_REF_DIV_MASK 0x3FF 269*4882a593Smuzhiyun #define PPLL_FB3_DIV_MASK 0x7FF 270*4882a593Smuzhiyun #define PPLL_POST3_DIV_MASK 0x70000 271*4882a593Smuzhiyun #define PPLL_ATOMIC_UPDATE_R 0x8000 272*4882a593Smuzhiyun #define PPLL_ATOMIC_UPDATE_W 0x8000 273*4882a593Smuzhiyun #define MEM_CFG_TYPE_MASK 0x3 274*4882a593Smuzhiyun #define XCLK_SRC_SEL_MASK 0x7 275*4882a593Smuzhiyun #define XPLL_FB_DIV_MASK 0xFF00 276*4882a593Smuzhiyun #define X_MPLL_REF_DIV_MASK 0xFF 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* CRTC control values (CRTC_GEN_CNTL) */ 279*4882a593Smuzhiyun #define CRTC_CSYNC_EN 0x00000010 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun #define CRTC2_DBL_SCAN_EN 0x00000001 282*4882a593Smuzhiyun #define CRTC2_DISPLAY_DIS 0x00800000 283*4882a593Smuzhiyun #define CRTC2_FIFO_EXTSENSE 0x00200000 284*4882a593Smuzhiyun #define CRTC2_ICON_EN 0x00100000 285*4882a593Smuzhiyun #define CRTC2_CUR_EN 0x00010000 286*4882a593Smuzhiyun #define CRTC2_EN 0x02000000 287*4882a593Smuzhiyun #define CRTC2_DISP_REQ_EN_B 0x04000000 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_MASK 0x00000700 290*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_4BPP 0x00000100 291*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_8BPP 0x00000200 292*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_15BPP 0x00000300 293*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_16BPP 0x00000400 294*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_24BPP 0x00000500 295*4882a593Smuzhiyun #define CRTC_PIX_WIDTH_32BPP 0x00000600 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun /* DAC_CNTL bit constants */ 298*4882a593Smuzhiyun #define DAC_8BIT_EN 0x00000100 299*4882a593Smuzhiyun #define DAC_MASK 0xFF000000 300*4882a593Smuzhiyun #define DAC_BLANKING 0x00000004 301*4882a593Smuzhiyun #define DAC_RANGE_CNTL 0x00000003 302*4882a593Smuzhiyun #define DAC_CLK_SEL 0x00000010 303*4882a593Smuzhiyun #define DAC_PALETTE_ACCESS_CNTL 0x00000020 304*4882a593Smuzhiyun #define DAC_PALETTE2_SNOOP_EN 0x00000040 305*4882a593Smuzhiyun #define DAC_PDWN 0x00008000 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* CRTC_EXT_CNTL */ 308*4882a593Smuzhiyun #define CRT_CRTC_ON 0x00008000 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* GEN_RESET_CNTL bit constants */ 311*4882a593Smuzhiyun #define SOFT_RESET_GUI 0x00000001 312*4882a593Smuzhiyun #define SOFT_RESET_VCLK 0x00000100 313*4882a593Smuzhiyun #define SOFT_RESET_PCLK 0x00000200 314*4882a593Smuzhiyun #define SOFT_RESET_ECP 0x00000400 315*4882a593Smuzhiyun #define SOFT_RESET_DISPENG_XCLK 0x00000800 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* PC_GUI_CTLSTAT bit constants */ 318*4882a593Smuzhiyun #define PC_BUSY_INIT 0x10000000 319*4882a593Smuzhiyun #define PC_BUSY_GUI 0x20000000 320*4882a593Smuzhiyun #define PC_BUSY_NGUI 0x40000000 321*4882a593Smuzhiyun #define PC_BUSY 0x80000000 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun #define BUS_MASTER_DIS 0x00000040 324*4882a593Smuzhiyun #define PM4_BUFFER_CNTL_NONPM4 0x00000000 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* DP_DATATYPE bit constants */ 327*4882a593Smuzhiyun #define DST_8BPP 0x00000002 328*4882a593Smuzhiyun #define DST_15BPP 0x00000003 329*4882a593Smuzhiyun #define DST_16BPP 0x00000004 330*4882a593Smuzhiyun #define DST_24BPP 0x00000005 331*4882a593Smuzhiyun #define DST_32BPP 0x00000006 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun #define BRUSH_SOLIDCOLOR 0x00000d00 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun /* DP_GUI_MASTER_CNTL bit constants */ 336*4882a593Smuzhiyun #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 337*4882a593Smuzhiyun #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 338*4882a593Smuzhiyun #define GMC_SRC_CLIP_DEFAULT 0x00000000 339*4882a593Smuzhiyun #define GMC_DST_CLIP_DEFAULT 0x00000000 340*4882a593Smuzhiyun #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 341*4882a593Smuzhiyun #define GMC_SRC_DSTCOLOR 0x00003000 342*4882a593Smuzhiyun #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 343*4882a593Smuzhiyun #define GMC_DP_SRC_RECT 0x02000000 344*4882a593Smuzhiyun #define GMC_3D_FCN_EN_CLR 0x00000000 345*4882a593Smuzhiyun #define GMC_AUX_CLIP_CLEAR 0x20000000 346*4882a593Smuzhiyun #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 347*4882a593Smuzhiyun #define GMC_WRITE_MASK_SET 0x40000000 348*4882a593Smuzhiyun #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun /* DP_GUI_MASTER_CNTL ROP3 named constants */ 351*4882a593Smuzhiyun #define ROP3_PATCOPY 0x00f00000 352*4882a593Smuzhiyun #define ROP3_SRCCOPY 0x00cc0000 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun #define SRC_DSTCOLOR 0x00030000 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun /* DP_CNTL bit constants */ 357*4882a593Smuzhiyun #define DST_X_RIGHT_TO_LEFT 0x00000000 358*4882a593Smuzhiyun #define DST_X_LEFT_TO_RIGHT 0x00000001 359*4882a593Smuzhiyun #define DST_Y_BOTTOM_TO_TOP 0x00000000 360*4882a593Smuzhiyun #define DST_Y_TOP_TO_BOTTOM 0x00000002 361*4882a593Smuzhiyun #define DST_X_MAJOR 0x00000000 362*4882a593Smuzhiyun #define DST_Y_MAJOR 0x00000004 363*4882a593Smuzhiyun #define DST_X_TILE 0x00000008 364*4882a593Smuzhiyun #define DST_Y_TILE 0x00000010 365*4882a593Smuzhiyun #define DST_LAST_PEL 0x00000020 366*4882a593Smuzhiyun #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 367*4882a593Smuzhiyun #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 368*4882a593Smuzhiyun #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 369*4882a593Smuzhiyun #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 370*4882a593Smuzhiyun #define DST_BRES_SIGN 0x00000100 371*4882a593Smuzhiyun #define DST_HOST_BIG_ENDIAN_EN 0x00000200 372*4882a593Smuzhiyun #define DST_POLYLINE_NONLAST 0x00008000 373*4882a593Smuzhiyun #define DST_RASTER_STALL 0x00010000 374*4882a593Smuzhiyun #define DST_POLY_EDGE 0x00040000 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun /* DP_MIX bit constants */ 377*4882a593Smuzhiyun #define DP_SRC_RECT 0x00000200 378*4882a593Smuzhiyun #define DP_SRC_HOST 0x00000300 379*4882a593Smuzhiyun #define DP_SRC_HOST_BYTEALIGN 0x00000400 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun /* LVDS_GEN_CNTL constants */ 382*4882a593Smuzhiyun #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 383*4882a593Smuzhiyun #define LVDS_BL_MOD_LEVEL_SHIFT 8 384*4882a593Smuzhiyun #define LVDS_BL_MOD_EN 0x00010000 385*4882a593Smuzhiyun #define LVDS_DIGION 0x00040000 386*4882a593Smuzhiyun #define LVDS_BLON 0x00080000 387*4882a593Smuzhiyun #define LVDS_ON 0x00000001 388*4882a593Smuzhiyun #define LVDS_DISPLAY_DIS 0x00000002 389*4882a593Smuzhiyun #define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004 390*4882a593Smuzhiyun #define LVDS_PANEL_24BITS_TFT 0x00000008 391*4882a593Smuzhiyun #define LVDS_FRAME_MOD_NO 0x00000000 392*4882a593Smuzhiyun #define LVDS_FRAME_MOD_2_LEVELS 0x00000010 393*4882a593Smuzhiyun #define LVDS_FRAME_MOD_4_LEVELS 0x00000020 394*4882a593Smuzhiyun #define LVDS_RST_FM 0x00000040 395*4882a593Smuzhiyun #define LVDS_EN 0x00000080 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun /* CRTC2_GEN_CNTL constants */ 398*4882a593Smuzhiyun #define CRTC2_EN 0x02000000 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun /* POWER_MANAGEMENT constants */ 401*4882a593Smuzhiyun #define PWR_MGT_ON 0x00000001 402*4882a593Smuzhiyun #define PWR_MGT_MODE_MASK 0x00000006 403*4882a593Smuzhiyun #define PWR_MGT_MODE_PIN 0x00000000 404*4882a593Smuzhiyun #define PWR_MGT_MODE_REGISTER 0x00000002 405*4882a593Smuzhiyun #define PWR_MGT_MODE_TIMER 0x00000004 406*4882a593Smuzhiyun #define PWR_MGT_MODE_PCI 0x00000006 407*4882a593Smuzhiyun #define PWR_MGT_AUTO_PWR_UP_EN 0x00000008 408*4882a593Smuzhiyun #define PWR_MGT_ACTIVITY_PIN_ON 0x00000010 409*4882a593Smuzhiyun #define PWR_MGT_STANDBY_POL 0x00000020 410*4882a593Smuzhiyun #define PWR_MGT_SUSPEND_POL 0x00000040 411*4882a593Smuzhiyun #define PWR_MGT_SELF_REFRESH 0x00000080 412*4882a593Smuzhiyun #define PWR_MGT_ACTIVITY_PIN_EN 0x00000100 413*4882a593Smuzhiyun #define PWR_MGT_KEYBD_SNOOP 0x00000200 414*4882a593Smuzhiyun #define PWR_MGT_TRISTATE_MEM_EN 0x00000800 415*4882a593Smuzhiyun #define PWR_MGT_SELW4MS 0x00001000 416*4882a593Smuzhiyun #define PWR_MGT_SLOWDOWN_MCLK 0x00002000 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun #define PMI_PMSCR_REG 0x60 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun /* used by ATI bug fix for hardware ROM */ 421*4882a593Smuzhiyun #define RAGE128_MPP_TB_CONFIG 0x01c0 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun #endif /* REG_RAGE128_H */ 424