Searched refs:PCI_BRIDGE_CTL_BUS_RESET (Results 1 – 13 of 13) sorted by relevance
57 bridge_ctl |= PCI_BRIDGE_CTL_BUS_RESET; in adf_reset_sbr()60 bridge_ctl &= ~PCI_BRIDGE_CTL_BUS_RESET; in adf_reset_sbr()
187 val |= PCI_BRIDGE_CTL_BUS_RESET; in hl_pci_reset_link_through_bridge()191 val &= ~(PCI_BRIDGE_CTL_BUS_RESET); in hl_pci_reset_link_through_bridge()
794 val |= PCI_BRIDGE_CTL_BUS_RESET << 16; in advk_pci_bridge_emul_base_conf_read()796 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16); in advk_pci_bridge_emul_base_conf_read()818 if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { in advk_pci_bridge_emul_base_conf_write()820 if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16)) in advk_pci_bridge_emul_base_conf_write()
195 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; in ls_pcie_g4_reset()
164 PCI_BRIDGE_CTL_BUS_RESET |
4901 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; in pci_reset_secondary_bus()4910 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; in pci_reset_secondary_bus()
303 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK); in pcibios_fixup_bus()
166 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ macro
825 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; in __pnv_eeh_bridge_reset()832 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; in __pnv_eeh_bridge_reset()
1323 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; in stex_hard_reset()1331 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; in stex_hard_reset()
272 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ macro