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Searched refs:ODPG_DATA_CONTROL_REG (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_bist.c44 ODPG_DATA_CONTROL_REG, 0x1, 0x1)); in ddr3_tip_bist_activate()
47 ODPG_DATA_CONTROL_REG, in ddr3_tip_bist_activate()
119 ODPG_DATA_CONTROL_REG, 0, in ddr3_tip_bist_activate()
131 ODPG_DATA_CONTROL_REG, 0, in ddr3_tip_bist_activate()
H A Dddr3_training_ip_engine.c221 ODPG_DATA_CONTROL_REG, in ddr3_tip_ip_training()
230 ODPG_DATA_CONTROL_REG, 0x3 | cs_num << 26, in ddr3_tip_ip_training()
470 ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS)); in ddr3_tip_ip_training()
531 ODPG_DATA_CONTROL_REG, data_value, 0xaffffffc); in ddr3_tip_configure_odpg()
613 ODPG_DATA_CONTROL_REG, (cs_num_type << 26), (3 << 26))); in ddr3_tip_read_training_result()
817 ODPG_DATA_CONTROL_REG, reg_data, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
821 ODPG_DATA_CONTROL_REG, (0x1 | (effective_cs << 26)), in ddr3_tip_load_pattern_to_mem()
856 ODPG_DATA_CONTROL_REG, (0x1 << 30), (u32) (0x3 << 30))); in ddr3_tip_load_pattern_to_mem()
861 ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS)); in ddr3_tip_load_pattern_to_mem()
H A Dddr3_training_leveling.c187 ODPG_DATA_CONTROL_REG, 0x3, 0x3)); in ddr3_tip_dynamic_read_leveling()
321 ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
378 ODPG_DATA_CONTROL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
387 ODPG_DATA_CONTROL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_read_leveling()
588 ODPG_DATA_CONTROL_REG, 0x3, 0x3)); in ddr3_tip_dynamic_per_bit_read_leveling()
720 ODPG_DATA_CONTROL_REG, 0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
885 ODPG_DATA_CONTROL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
893 ODPG_DATA_CONTROL_REG, 0x0, MASK_ALL_BITS)); in ddr3_tip_dynamic_per_bit_read_leveling()
H A Dddr3_training_ip_flow.h144 #define ODPG_DATA_CONTROL_REG 0x1630 macro