Searched refs:NUM_CRYSTAL_FREQ (Results 1 – 4 of 4) sorted by relevance
107 extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS];108 extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ];109 extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ];110 extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ];111 extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ];112 extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ];
75 #define NUM_CRYSTAL_FREQ 0x4 macro
60 const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS] = {95 const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ] = {102 const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ] = {109 const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {116 const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {123 const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ] = {
54 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {89 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {96 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {103 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = {