1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * clock.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * clock header 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _CLOCKS_H_ 12*4882a593Smuzhiyun #define _CLOCKS_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <asm/arch/clocks_am33xx.h> 15*4882a593Smuzhiyun #include <asm/arch/hardware.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) 18*4882a593Smuzhiyun #include <asm/arch/clock_ti81xx.h> 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define LDELAY 1000000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /*CM_<clock_domain>__CLKCTRL */ 24*4882a593Smuzhiyun #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 25*4882a593Smuzhiyun #define CD_CLKCTRL_CLKTRCTRL_MASK 3 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 28*4882a593Smuzhiyun #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 29*4882a593Smuzhiyun #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* CM_<clock_domain>_<module>_CLKCTRL */ 32*4882a593Smuzhiyun #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 33*4882a593Smuzhiyun #define MODULE_CLKCTRL_MODULEMODE_MASK 3 34*4882a593Smuzhiyun #define MODULE_CLKCTRL_IDLEST_SHIFT 16 35*4882a593Smuzhiyun #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 38*4882a593Smuzhiyun #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 41*4882a593Smuzhiyun #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 42*4882a593Smuzhiyun #define MODULE_CLKCTRL_IDLEST_IDLE 2 43*4882a593Smuzhiyun #define MODULE_CLKCTRL_IDLEST_DISABLED 3 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* CM_CLKMODE_DPLL */ 46*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_SSC_EN_SHIFT 12 47*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_SSC_EN_MASK (1 << 12) 48*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_SSC_ACK_MASK (1 << 13) 49*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 50*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_SSC_TYPE_MASK (1 << 15) 51*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 52*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 53*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 54*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 55*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 56*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 57*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 58*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 59*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 60*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 61*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_EN_SHIFT 0 62*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 65*4882a593Smuzhiyun #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define DPLL_EN_STOP 1 68*4882a593Smuzhiyun #define DPLL_EN_MN_BYPASS 4 69*4882a593Smuzhiyun #define DPLL_EN_LOW_POWER_BYPASS 5 70*4882a593Smuzhiyun #define DPLL_EN_LOCK 7 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* CM_IDLEST_DPLL fields */ 73*4882a593Smuzhiyun #define ST_DPLL_CLK_MASK 1 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* CM_CLKSEL_DPLL */ 76*4882a593Smuzhiyun #define CM_CLKSEL_DPLL_M_SHIFT 8 77*4882a593Smuzhiyun #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 78*4882a593Smuzhiyun #define CM_CLKSEL_DPLL_N_SHIFT 0 79*4882a593Smuzhiyun #define CM_CLKSEL_DPLL_N_MASK 0x7F 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct dpll_params { 82*4882a593Smuzhiyun u32 m; 83*4882a593Smuzhiyun u32 n; 84*4882a593Smuzhiyun s8 m2; 85*4882a593Smuzhiyun s8 m3; 86*4882a593Smuzhiyun s8 m4; 87*4882a593Smuzhiyun s8 m5; 88*4882a593Smuzhiyun s8 m6; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun struct dpll_regs { 92*4882a593Smuzhiyun u32 cm_clkmode_dpll; 93*4882a593Smuzhiyun u32 cm_idlest_dpll; 94*4882a593Smuzhiyun u32 cm_autoidle_dpll; 95*4882a593Smuzhiyun u32 cm_clksel_dpll; 96*4882a593Smuzhiyun u32 cm_div_m2_dpll; 97*4882a593Smuzhiyun u32 cm_div_m3_dpll; 98*4882a593Smuzhiyun u32 cm_div_m4_dpll; 99*4882a593Smuzhiyun u32 cm_div_m5_dpll; 100*4882a593Smuzhiyun u32 cm_div_m6_dpll; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun extern const struct dpll_regs dpll_mpu_regs; 104*4882a593Smuzhiyun extern const struct dpll_regs dpll_core_regs; 105*4882a593Smuzhiyun extern const struct dpll_regs dpll_per_regs; 106*4882a593Smuzhiyun extern const struct dpll_regs dpll_ddr_regs; 107*4882a593Smuzhiyun extern const struct dpll_params dpll_mpu_opp[NUM_CRYSTAL_FREQ][NUM_OPPS]; 108*4882a593Smuzhiyun extern const struct dpll_params dpll_core_1000MHz[NUM_CRYSTAL_FREQ]; 109*4882a593Smuzhiyun extern const struct dpll_params dpll_per_192MHz[NUM_CRYSTAL_FREQ]; 110*4882a593Smuzhiyun extern const struct dpll_params dpll_ddr2_266MHz[NUM_CRYSTAL_FREQ]; 111*4882a593Smuzhiyun extern const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ]; 112*4882a593Smuzhiyun extern const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ]; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun extern struct cm_wkuppll *const cmwkup; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun const struct dpll_params *get_dpll_mpu_params(void); 117*4882a593Smuzhiyun const struct dpll_params *get_dpll_core_params(void); 118*4882a593Smuzhiyun const struct dpll_params *get_dpll_per_params(void); 119*4882a593Smuzhiyun const struct dpll_params *get_dpll_ddr_params(void); 120*4882a593Smuzhiyun void scale_vcores(void); 121*4882a593Smuzhiyun void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); 122*4882a593Smuzhiyun void prcm_init(void); 123*4882a593Smuzhiyun void enable_basic_clocks(void); 124*4882a593Smuzhiyun void do_enable_clocks(u32 *const *, u32 *const *, u8); 125*4882a593Smuzhiyun void do_disable_clocks(u32 *const *, u32 *const *, u8); 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun void set_mpu_spreadspectrum(int permille); 128*4882a593Smuzhiyun #endif 129