1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * hardware.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * hardware specific header 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __AM33XX_HARDWARE_H 12*4882a593Smuzhiyun #define __AM33XX_HARDWARE_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <config.h> 15*4882a593Smuzhiyun #include <asm/arch/omap.h> 16*4882a593Smuzhiyun #ifdef CONFIG_AM33XX 17*4882a593Smuzhiyun #include <asm/arch/hardware_am33xx.h> 18*4882a593Smuzhiyun #elif defined(CONFIG_TI816X) 19*4882a593Smuzhiyun #include <asm/arch/hardware_ti816x.h> 20*4882a593Smuzhiyun #elif defined(CONFIG_TI814X) 21*4882a593Smuzhiyun #include <asm/arch/hardware_ti814x.h> 22*4882a593Smuzhiyun #elif defined(CONFIG_AM43XX) 23*4882a593Smuzhiyun #include <asm/arch/hardware_am43xx.h> 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Common hardware definitions 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* DM Timer base addresses */ 31*4882a593Smuzhiyun #define DM_TIMER0_BASE 0x4802C000 32*4882a593Smuzhiyun #define DM_TIMER1_BASE 0x4802E000 33*4882a593Smuzhiyun #define DM_TIMER2_BASE 0x48040000 34*4882a593Smuzhiyun #define DM_TIMER3_BASE 0x48042000 35*4882a593Smuzhiyun #define DM_TIMER4_BASE 0x48044000 36*4882a593Smuzhiyun #define DM_TIMER5_BASE 0x48046000 37*4882a593Smuzhiyun #define DM_TIMER6_BASE 0x48048000 38*4882a593Smuzhiyun #define DM_TIMER7_BASE 0x4804A000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* GPIO Base address */ 41*4882a593Smuzhiyun #define GPIO0_BASE 0x48032000 42*4882a593Smuzhiyun #define GPIO1_BASE 0x4804C000 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* BCH Error Location Module */ 45*4882a593Smuzhiyun #define ELM_BASE 0x48080000 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* EMIF Base address */ 48*4882a593Smuzhiyun #define EMIF4_0_CFG_BASE 0x4C000000 49*4882a593Smuzhiyun #define EMIF4_1_CFG_BASE 0x4D000000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* DDR Base address */ 52*4882a593Smuzhiyun #define DDR_CTRL_ADDR 0x44E10E04 53*4882a593Smuzhiyun #define DDR_CONTROL_BASE_ADDR 0x44E11404 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* UART */ 56*4882a593Smuzhiyun #define DEFAULT_UART_BASE UART0_BASE 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* GPMC Base address */ 59*4882a593Smuzhiyun #define GPMC_BASE 0x50000000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* CPSW Config space */ 62*4882a593Smuzhiyun #define CPSW_BASE 0x4A100000 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Control status register */ 65*4882a593Smuzhiyun #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) 66*4882a593Smuzhiyun #define CTRL_CRYSTAL_FREQ_SRC_SHIFT 31 67*4882a593Smuzhiyun #define CTRL_CRYSTAL_FREQ_SELECTION_MASK (0x3 << 29) 68*4882a593Smuzhiyun #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT 29 69*4882a593Smuzhiyun #define CTRL_SYSBOOT_15_14_MASK (0x3 << 22) 70*4882a593Smuzhiyun #define CTRL_SYSBOOT_15_14_SHIFT 22 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT 0x0 73*4882a593Smuzhiyun #define CTRL_CRYSTAL_FREQ_SRC_EFUSE 0x1 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define NUM_CRYSTAL_FREQ 0x4 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun int clk_get(int clk); 78*4882a593Smuzhiyun #endif /* __AM33XX_HARDWARE_H */ 79